DE69521954T2 - Herstellungsverfahren einer Halbleiterpackungsanordnung mit Chipumfang - Google Patents

Herstellungsverfahren einer Halbleiterpackungsanordnung mit Chipumfang

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Publication number
DE69521954T2
DE69521954T2 DE69521954T DE69521954T DE69521954T2 DE 69521954 T2 DE69521954 T2 DE 69521954T2 DE 69521954 T DE69521954 T DE 69521954T DE 69521954 T DE69521954 T DE 69521954T DE 69521954 T2 DE69521954 T2 DE 69521954T2
Authority
DE
Germany
Prior art keywords
manufacturing process
semiconductor package
chip size
package arrangement
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69521954T
Other languages
English (en)
Other versions
DE69521954D1 (de
Inventor
Keiichiro Kata
Shuichi Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69521954D1 publication Critical patent/DE69521954D1/de
Application granted granted Critical
Publication of DE69521954T2 publication Critical patent/DE69521954T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
DE69521954T 1994-09-30 1995-09-29 Herstellungsverfahren einer Halbleiterpackungsanordnung mit Chipumfang Expired - Fee Related DE69521954T2 (de)

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EP0704899A3 (de) 1997-08-20
EP0704899B1 (de) 2001-08-01
DE69521954D1 (de) 2001-09-06
CN1066574C (zh) 2001-05-30
KR100209994B1 (ko) 1999-07-15
CA2159243C (en) 2000-06-13
KR960012397A (ko) 1996-04-20
JP2581017B2 (ja) 1997-02-12
JPH08102474A (ja) 1996-04-16
CA2159243A1 (en) 1996-03-31
US5897337A (en) 1999-04-27
CN1128901A (zh) 1996-08-14
EP0704899A2 (de) 1996-04-03

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