FR2800198B1 - Procede de protection de puces de circuit integre par aspiration sous vide - Google Patents
Procede de protection de puces de circuit integre par aspiration sous videInfo
- Publication number
- FR2800198B1 FR2800198B1 FR9913371A FR9913371A FR2800198B1 FR 2800198 B1 FR2800198 B1 FR 2800198B1 FR 9913371 A FR9913371 A FR 9913371A FR 9913371 A FR9913371 A FR 9913371A FR 2800198 B1 FR2800198 B1 FR 2800198B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- circuit chips
- vacuum suction
- support sheets
- protecting integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 239000012777 electrically insulating material Substances 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 239000004840 adhesive resin Substances 0.000 abstract 1
- 229920006223 adhesive resin Polymers 0.000 abstract 1
- 239000012530 fluid Substances 0.000 abstract 1
- 239000002966 varnish Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Wire Bonding (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9913371A FR2800198B1 (fr) | 1999-10-26 | 1999-10-26 | Procede de protection de puces de circuit integre par aspiration sous vide |
PCT/FR2000/002793 WO2001031702A1 (fr) | 1999-10-26 | 2000-10-09 | Procede de protection de puces de circuit integre par depot d'une couche electriquement isolante par aspirante sous vide |
AU77961/00A AU7796100A (en) | 1999-10-26 | 2000-10-09 | Method for protecting integrated card chips by deposit of an electrically insulating layer by vacuum suction |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9913371A FR2800198B1 (fr) | 1999-10-26 | 1999-10-26 | Procede de protection de puces de circuit integre par aspiration sous vide |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2800198A1 FR2800198A1 (fr) | 2001-04-27 |
FR2800198B1 true FR2800198B1 (fr) | 2002-03-29 |
Family
ID=9551370
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9913371A Expired - Fee Related FR2800198B1 (fr) | 1999-10-26 | 1999-10-26 | Procede de protection de puces de circuit integre par aspiration sous vide |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU7796100A (fr) |
FR (1) | FR2800198B1 (fr) |
WO (1) | WO2001031702A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10706344B1 (en) * | 2017-05-23 | 2020-07-07 | Fiteq, Inc. | Process for maintaining registration of an array through use of a carrier in process flow |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2348323A1 (de) * | 1973-09-26 | 1975-04-03 | Licentia Gmbh | Integrierte festkoerperschaltung mit einer vielzahl von bauelementen in einem gemeinsamen halbleiterkoerper |
GB2120861B (en) * | 1982-05-27 | 1985-10-02 | Vladimir Iosifovich Livshits | Process for manufacturing panels to be used in microelectronic systems |
US5270260A (en) * | 1990-08-23 | 1993-12-14 | Siemens Aktiengesellschaft | Method and apparatus for connecting a semiconductor chip to a carrier system |
JP2980495B2 (ja) * | 1993-09-07 | 1999-11-22 | 株式会社東芝 | 半導体装置の製造方法 |
JP2581017B2 (ja) * | 1994-09-30 | 1997-02-12 | 日本電気株式会社 | 半導体装置及びその製造方法 |
FR2761498B1 (fr) * | 1997-03-27 | 1999-06-18 | Gemplus Card Int | Module electronique et son procede de fabrication et carte a puce comportant un tel module |
FR2761497B1 (fr) * | 1997-03-27 | 1999-06-18 | Gemplus Card Int | Procede de fabrication d'une carte a puce ou analogue |
DE19845296A1 (de) * | 1998-09-03 | 2000-03-16 | Fraunhofer Ges Forschung | Verfahren zur Kontaktierung eines Schaltungschips |
-
1999
- 1999-10-26 FR FR9913371A patent/FR2800198B1/fr not_active Expired - Fee Related
-
2000
- 2000-10-09 WO PCT/FR2000/002793 patent/WO2001031702A1/fr active Application Filing
- 2000-10-09 AU AU77961/00A patent/AU7796100A/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
AU7796100A (en) | 2001-05-08 |
FR2800198A1 (fr) | 2001-04-27 |
WO2001031702A1 (fr) | 2001-05-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse | ||
D3 | Decision to revoke the decision of lapse | ||
RN | Application for restoration | ||
ST | Notification of lapse |