DE69418020D1 - Ausgangspufferkreis, Eingangspufferkreis und Zweirichtungspufferkreis für mehrere Spannungssysteme - Google Patents

Ausgangspufferkreis, Eingangspufferkreis und Zweirichtungspufferkreis für mehrere Spannungssysteme

Info

Publication number
DE69418020D1
DE69418020D1 DE69418020T DE69418020T DE69418020D1 DE 69418020 D1 DE69418020 D1 DE 69418020D1 DE 69418020 T DE69418020 T DE 69418020T DE 69418020 T DE69418020 T DE 69418020T DE 69418020 D1 DE69418020 D1 DE 69418020D1
Authority
DE
Germany
Prior art keywords
buffer circuit
bidirectional
voltage systems
several voltage
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69418020T
Other languages
English (en)
Other versions
DE69418020T2 (de
Inventor
Kenichiro Kobayashi
Hisaya Keida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KAWASAKI STEEL MICROELECTRONICS, INC., CHIBA, JP
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=18195941&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69418020(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Publication of DE69418020D1 publication Critical patent/DE69418020D1/de
Application granted granted Critical
Publication of DE69418020T2 publication Critical patent/DE69418020T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018592—Coupling arrangements; Interface arrangements using field effect transistors only with a bidirectional operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Electromagnetism (AREA)
  • Automation & Control Theory (AREA)
  • Radar, Positioning & Navigation (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
DE69418020T 1993-12-24 1994-12-22 Ausgangspufferkreis, Eingangspufferkreis und Zweirichtungspufferkreis für mehrere Spannungssysteme Expired - Fee Related DE69418020T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32715693A JP3562725B2 (ja) 1993-12-24 1993-12-24 出力バッファ回路、および入出力バッファ回路

Publications (2)

Publication Number Publication Date
DE69418020D1 true DE69418020D1 (de) 1999-05-27
DE69418020T2 DE69418020T2 (de) 1999-08-12

Family

ID=18195941

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69430492T Expired - Fee Related DE69430492T2 (de) 1993-12-24 1994-12-22 Eingangs-Buffer und bidirektionaler Buffer für Systeme mit mehreren Spannungen
DE69418020T Expired - Fee Related DE69418020T2 (de) 1993-12-24 1994-12-22 Ausgangspufferkreis, Eingangspufferkreis und Zweirichtungspufferkreis für mehrere Spannungssysteme

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69430492T Expired - Fee Related DE69430492T2 (de) 1993-12-24 1994-12-22 Eingangs-Buffer und bidirektionaler Buffer für Systeme mit mehreren Spannungen

Country Status (7)

Country Link
US (1) US5532621A (de)
EP (2) EP0844737B1 (de)
JP (1) JP3562725B2 (de)
KR (1) KR100326654B1 (de)
CN (1) CN1108017A (de)
CA (1) CA2139008A1 (de)
DE (2) DE69430492T2 (de)

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WO1996042139A1 (en) * 1995-06-13 1996-12-27 Advanced Micro Devices, Inc. Input receiver, output driver, and input/output driver circuits capable of high voltage operation for an integrated circuit
DE19536020C1 (de) * 1995-09-27 1997-02-20 Siemens Ag Bidirektionale Treiberschaltung für PCI-Bussysteme
JP2806335B2 (ja) * 1996-01-17 1998-09-30 日本電気株式会社 論理回路及びこれを用いた半導体集積回路
JP3340906B2 (ja) * 1996-03-13 2002-11-05 株式会社 沖マイクロデザイン 出力回路
US6147511A (en) 1996-05-28 2000-11-14 Altera Corporation Overvoltage-tolerant interface for integrated circuits
JP3234778B2 (ja) * 1996-09-25 2001-12-04 株式会社東芝 入出力回路及びこの入出力回路への信号の入出力方法
US5933025A (en) * 1997-01-15 1999-08-03 Xilinx, Inc. Low voltage interface circuit with a high voltage tolerance
US5889420A (en) * 1997-06-30 1999-03-30 Siemens Aktiengesellschaft OCD with low output capacitance
US6255850B1 (en) * 1997-10-28 2001-07-03 Altera Corporation Integrated circuit with both clamp protection and high impedance protection from input overshoot
US6043680A (en) * 1998-02-02 2000-03-28 Tritech Microelectronics, Ltd. 5V tolerant I/O buffer
US6121795A (en) * 1998-02-26 2000-09-19 Xilinx, Inc. Low-voltage input/output circuit with high voltage tolerance
US6141200A (en) * 1998-04-20 2000-10-31 International Business Machines Corporation Stacked PFET off-chip driver with a latch bias generator for overvoltage protection
US6445039B1 (en) 1998-11-12 2002-09-03 Broadcom Corporation System and method for ESD Protection
US6885275B1 (en) 1998-11-12 2005-04-26 Broadcom Corporation Multi-track integrated spiral inductor
US6985035B1 (en) 1998-11-12 2006-01-10 Broadcom Corporation System and method for linearizing a CMOS differential pair
US8405152B2 (en) 1999-01-15 2013-03-26 Broadcom Corporation System and method for ESD protection
US7687858B2 (en) 1999-01-15 2010-03-30 Broadcom Corporation System and method for ESD protection
AU3209000A (en) 1999-01-15 2000-08-01 Broadcom Corporation System and method for esd protection
US7696823B2 (en) 1999-05-26 2010-04-13 Broadcom Corporation System and method for linearizing a CMOS differential pair
DE60027899T2 (de) 1999-06-29 2006-12-28 Broadcom Corp., Irvine System und verfahren zur unabhängigen versorgungsfolge integrierter schaltungen
US6353333B1 (en) * 2000-06-16 2002-03-05 Xilinx, Inc. Simplified 5V tolerance circuit for 3.3V I/O design
WO2002027916A1 (fr) * 2000-09-26 2002-04-04 Seiko Epson Corporation Circuit d'oscillation, circuit electronique et dispositif semi-conducteur, horloge, et appareil electronique comprenant ces circuits
JP3742335B2 (ja) * 2001-12-20 2006-02-01 富士通株式会社 入出力バッファ回路
US6690191B2 (en) 2001-12-21 2004-02-10 Sun Microsystems, Inc. Bi-directional output buffer
KR100532433B1 (ko) * 2003-05-07 2005-11-30 삼성전자주식회사 하나의 패드를 통하여 데이터를 동시에 입출력하기 위한장치 및 방법
DE60327718D1 (de) * 2003-05-28 2009-07-02 Fujitsu Microelectronics Ltd Halbleiterbauelement
KR100711108B1 (ko) * 2004-07-16 2007-04-24 삼성전자주식회사 레벨 쉬프터 및 레벨 쉬프팅 방법
US7439592B2 (en) 2004-12-13 2008-10-21 Broadcom Corporation ESD protection for high voltage applications
US7505238B2 (en) 2005-01-07 2009-03-17 Agnes Neves Woo ESD configuration for low parasitic capacitance I/O
US7429882B2 (en) * 2006-06-08 2008-09-30 Toshiba America Electronic Components, Inc. AC-DC input buffer
KR101548242B1 (ko) * 2008-07-21 2015-09-04 삼성전자주식회사 반도체 장치의 출력구동장치, 이의 동작 방법, 및 이를 포함하는 전자 처리 장치
US7986171B2 (en) * 2008-10-21 2011-07-26 Himax Technologies Limited Mixed-voltage I/O buffer
US7893731B2 (en) * 2008-11-19 2011-02-22 Toshiba America Electronic Components, Inc. AC/DC input buffer
JP5189576B2 (ja) * 2009-10-05 2013-04-24 日本電波工業株式会社 電圧制御発振器
US8390320B2 (en) * 2011-03-10 2013-03-05 Infineon Technologies Ag Dynamic pad hardware control
CN103268133B (zh) * 2013-04-18 2014-12-10 北京大学 一种多工作电压输入输出管脚单元电路
US9473141B2 (en) * 2014-10-13 2016-10-18 Globalfoundries Inc. Receiving an I/O signal in multiple voltage domains
CN105790753B (zh) * 2014-12-25 2018-12-21 中芯国际集成电路制造(上海)有限公司 输出缓冲器
JP6719233B2 (ja) * 2016-03-07 2020-07-08 エイブリック株式会社 出力回路
TWI654842B (zh) * 2017-10-20 2019-03-21 立積電子股份有限公司 反相器
CN107733026B (zh) * 2017-10-30 2020-06-05 Oppo广东移动通信有限公司 一种负压保护电路、usb充电电路及终端设备
CN109102832B (zh) * 2018-09-12 2021-07-06 中国电子科技集团公司第五十八研究所 一种负向电压传输电路
US11019392B2 (en) * 2019-07-19 2021-05-25 Semiconductor Components Industries, Llc Methods and apparatus for an output buffer
US11726943B2 (en) * 2020-03-06 2023-08-15 Apogee Semiconductor, Inc. Circuits and methods for enabling redundancy in an electronic system employing cold-sparing

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US4217502A (en) * 1977-09-10 1980-08-12 Tokyo Shibaura Denki Kabushiki Kaisha Converter producing three output states
US4324991A (en) * 1979-12-12 1982-04-13 Casio Computer Co., Ltd. Voltage selector circuit
US4438352A (en) * 1980-06-02 1984-03-20 Xerox Corporation TTL Compatible CMOS input buffer
JPS6290020A (ja) * 1985-10-15 1987-04-24 Mitsubishi Electric Corp 半導体集積回路
JPH0728214B2 (ja) * 1987-02-06 1995-03-29 株式会社日立製作所 半導体集積回路装置
US4800303A (en) * 1987-05-19 1989-01-24 Gazelle Microcircuits, Inc. TTL compatible output buffer
JPH01317022A (ja) * 1988-06-16 1989-12-21 Toshiba Corp 電源切り換え回路
KR910007785B1 (ko) * 1988-12-20 1991-10-02 삼성전자 주식회사 전원공급전압 변동에 대해 안정한 씨모스 입력 버퍼회로
US4978905A (en) * 1989-10-31 1990-12-18 Cypress Semiconductor Corp. Noise reduction output buffer
JPH07111826B2 (ja) * 1990-09-12 1995-11-29 株式会社東芝 半導体記憶装置
US5151619A (en) * 1990-10-11 1992-09-29 International Business Machines Corporation Cmos off chip driver circuit
US5128560A (en) * 1991-03-22 1992-07-07 Micron Technology, Inc. Boosted supply output driver circuit for driving an all N-channel output stage
US5321319A (en) * 1992-06-08 1994-06-14 Advanced Micro Devices, Inc. High speed CMOS bus driver circuit that provides minimum output signal oscillation
KR940010674B1 (ko) * 1992-10-29 1994-10-24 삼성전자 주식회사 입력 버퍼

Also Published As

Publication number Publication date
EP0844737A3 (de) 1999-03-17
EP0844737A2 (de) 1998-05-27
DE69430492T2 (de) 2002-11-21
DE69418020T2 (de) 1999-08-12
EP0844737B1 (de) 2002-04-24
CN1108017A (zh) 1995-09-06
CA2139008A1 (en) 1995-06-25
JP3562725B2 (ja) 2004-09-08
EP0663727B1 (de) 1999-04-21
US5532621A (en) 1996-07-02
KR100326654B1 (ko) 2002-06-28
DE69430492D1 (de) 2002-05-29
KR950022130A (ko) 1995-07-26
EP0663727A1 (de) 1995-07-19
JPH07183774A (ja) 1995-07-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KAWASAKI STEEL MICROELECTRONICS, INC., CHIBA, JP

8339 Ceased/non-payment of the annual fee