DE69620323D1 - Eingangspufferschaltung - Google Patents

Eingangspufferschaltung

Info

Publication number
DE69620323D1
DE69620323D1 DE69620323T DE69620323T DE69620323D1 DE 69620323 D1 DE69620323 D1 DE 69620323D1 DE 69620323 T DE69620323 T DE 69620323T DE 69620323 T DE69620323 T DE 69620323T DE 69620323 D1 DE69620323 D1 DE 69620323D1
Authority
DE
Germany
Prior art keywords
buffer circuit
input buffer
input
circuit
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69620323T
Other languages
English (en)
Other versions
DE69620323T2 (de
Inventor
Takayuki Shirai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69620323D1 publication Critical patent/DE69620323D1/de
Application granted granted Critical
Publication of DE69620323T2 publication Critical patent/DE69620323T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
DE69620323T 1995-08-30 1996-08-14 Eingangspufferschaltung Expired - Fee Related DE69620323T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7222385A JP2743878B2 (ja) 1995-08-30 1995-08-30 入力バッファ回路

Publications (2)

Publication Number Publication Date
DE69620323D1 true DE69620323D1 (de) 2002-05-08
DE69620323T2 DE69620323T2 (de) 2002-10-10

Family

ID=16781537

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69620323T Expired - Fee Related DE69620323T2 (de) 1995-08-30 1996-08-14 Eingangspufferschaltung

Country Status (5)

Country Link
US (1) US6140835A (de)
EP (1) EP0762290B1 (de)
JP (1) JP2743878B2 (de)
KR (1) KR100260989B1 (de)
DE (1) DE69620323T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3173489B2 (ja) * 1998-12-28 2001-06-04 日本電気株式会社 半導体集積回路
EP1071215A1 (de) * 1999-07-19 2001-01-24 STMicroelectronics S.r.l. Eingangsstufe mit dynamischer Hysteresis
US7187721B1 (en) * 2000-02-09 2007-03-06 Rambus Inc. Transition-time control in a high-speed data transmitter
US6489809B2 (en) * 2000-11-30 2002-12-03 Infineon Technologies Ag Circuit for receiving and driving a clock-signal
DE10302128B3 (de) * 2003-01-21 2004-09-09 Infineon Technologies Ag Pufferverstärkeranordnung
US20080054943A1 (en) * 2006-09-06 2008-03-06 Ravindraraj Ramaraju Variable switching point circuit
JP2008211707A (ja) * 2007-02-28 2008-09-11 Nec Electronics Corp 入力回路
KR100951658B1 (ko) * 2007-11-13 2010-04-07 주식회사 하이닉스반도체 신호 라인 제어 회로 및 그의 제어 방법
US7868666B2 (en) * 2009-04-08 2011-01-11 Fairchild Semiconductor Corporation Low-quiescent-current buffer
US8350612B2 (en) * 2009-10-30 2013-01-08 Himax Technologies Limited Circuit for resetting system and delay circuit
KR101062891B1 (ko) * 2010-02-26 2011-09-07 주식회사 하이닉스반도체 반도체 집적회로
US20120249184A1 (en) * 2011-03-30 2012-10-04 Qualcomm Incorporated Narrow pulse filter
US8902677B2 (en) * 2012-12-10 2014-12-02 Freescale Semiconductor, Inc. Reducing the power consumption of memory devices
US8942332B2 (en) * 2012-12-17 2015-01-27 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for data serialization and inter symbol interference reduction
US10033359B2 (en) * 2015-10-23 2018-07-24 Qualcomm Incorporated Area efficient flip-flop with improved scan hold-margin
US9966953B2 (en) 2016-06-02 2018-05-08 Qualcomm Incorporated Low clock power data-gated flip-flop
KR102665085B1 (ko) * 2022-02-08 2024-05-13 주식회사 피델릭스 히스테리시스 기능을 가지는 입력 버퍼 회로
US20230327652A1 (en) * 2022-04-11 2023-10-12 Renesas Electronics Corporation Semiconductor device and input signal controlling method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1460194A (en) * 1974-05-17 1976-12-31 Rca Corp Circuits exhibiting hysteresis
JPS59181829A (ja) * 1983-03-31 1984-10-16 Toshiba Corp 半導体素子の出力バツフア回路
US4672243A (en) * 1985-05-28 1987-06-09 American Telephone And Telegraph Company, At&T Bell Laboratories Zero standby current TTL to CMOS input buffer
JPH0389624A (ja) * 1989-08-31 1991-04-15 Fujitsu Ltd 半導体集積回路
JP3028569B2 (ja) * 1990-08-20 2000-04-04 日本電気株式会社 入力バッファ回路
JPH04139870A (ja) * 1990-10-01 1992-05-13 Nec Corp 入力バッファ回路
US5336942A (en) * 1992-08-12 1994-08-09 Western Digital (Singapore) Pty, Ltd. High speed Schmitt trigger with process, temperature and power supply independence
US5341033A (en) * 1992-11-23 1994-08-23 Analog Devices, Inc. Input buffer circuit with deglitch method and apparatus
JPH0729377A (ja) * 1993-07-08 1995-01-31 Sharp Corp 半導体記憶装置
US5654645A (en) * 1995-07-27 1997-08-05 Cypress Semiconductor Corp. Buffer with controlled hysteresis

Also Published As

Publication number Publication date
KR100260989B1 (ko) 2000-07-01
KR970012792A (ko) 1997-03-29
EP0762290B1 (de) 2002-04-03
US6140835A (en) 2000-10-31
DE69620323T2 (de) 2002-10-10
EP0762290A1 (de) 1997-03-12
JPH0962423A (ja) 1997-03-07
JP2743878B2 (ja) 1998-04-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee