WO1996042139A1

WO1996042139A1 - Input receiver, output driver, and input/output driver circuits capable of high voltage operation for an integrated circuit

Info

Publication number: WO1996042139A1
Application number: PCT/US1996/010297
Authority: WO
Inventors: Keith G. Hawkins; Shivachandra I. Javalagi; Harikumar B. Nair; Kuok Y. Ling; Donald G. Craycraft
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1995-06-13
Filing date: 1996-06-13
Publication date: 1996-12-27

Abstract

An output driver circuit and an input receiver circuit are provided. The output driver circuit employs a series-connected pair of PMOS transistors (102) and coupled to a series-connected pair of NMOS transistors (106, 108). One of the PMOS transistors (102) and one of the NMOS transistors (106) have their gate terminals connected to a pair of power sources (Vref, VCC) such that these transistors maintain a voltage level on the node connecting the transistor to its corresponding pair. The voltage level is maintained during times when the pair of transistors are not conducting current. By maintaining this voltage, the voltage difference between any two terminals of the transistors is held within the maximum allowable voltage of the semiconductor technology. An input receiver circuit is also described which contains an NMOS transistor (120) between the input conductor and receiving inverter circuits. This NMOS transistor (120) has its gate terminal connected to a power supply (VCC) conveying the same voltage as the power supply for the integrated circuit core. The NMOS transistor (120) limits the voltage at the input of the receiving inverter circuits to no more than the power supply voltage (VCC). The circuits may be combined to form an input/output driver circuit.

Description

TITLE: INPUT RECEIVER, OUTPUT DRIVER, AND INPUT/OUTPUT

DRIVER CIRCUITS CAPABLE OF HIGH VOLTAGE OPERATION FOR AN INTEGRATED CIRCUIT

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention is related to the field of driver and receiver circuits on an integrated circuit wherein the driver and receiver circuits are capable of receiving and driving a higher voltage than the voltage supplying the integrated circuit core.

2. Description of the Relevant Art

Integrated circuits are used in a wide variety of applications including computer systems, personal information devices such as cellular phones and electronic organizers, and automobile electronic control systems. As used herein, the term "integrated circuit" refers to any electronic device which embodies a predetermined set of functions upon a single monolithic substrate.

Integrated circuits may be fabricated in different semiconductor technologies. The selection of a particular semiconductor technology with which to fabricate a particular integrated circuit depends on many factors. The semiconductor technologies available when designing the particular integrated circuit in many ways dictate how the circuit will perform. The cost involved in fabricating the integrated circuit also determines circuit operability given the limited resources in many wafer fabrication sites. Considerations related to the application for which the integrated circuit is designed, such as operable temperature ranges and power consumption constraints imposed by circuit application may also affect the choice of semiconductor technology.

Complimentary metal-oxide-semiconductor (CMOS) technology is a particularly popular semiconductor technology for many applications. Two types of transistors may be formed in a CMOS process: PMOS transistors and NMOS transistors. PMOS transistors and NMOS transistors have four terminals (or connection points): a gate terminal, a source terminal, a drain terminal, and a bulk terminal. Electric current flows from the source terminal to the drain terminal of a transistor when a voltage applied to the gate terminal has either a higher or lower value than the voltage applied to the source terminal, depending on the transistor type. A PMOS transistor is a transistor in which current flows if the voltage applied to the gate terminal is lower than the voltage applied to the source terminal. An NMOS transistor is a transistor in which current flows if the voltage applied to the gate terminal is higher than the voltage applied to the source terminal. The bulk terminal is connected either to the source terminal or to a proper bias voltage.

In both the PMOS transistor and NMOS transistor, the difference in voltage between the gate terminal and the source terminal must be larger in absolute value than a certain voltage before current flow begins. This certain voltage is referred to as a "threshold" voltage and is the voltage required to form an energized channel between the source and the drain diffusion regions in the PMOS transistor or NMOS transistor. As will be appreciated by those skilled in the art, a transistor is formed on a substrate by diffusing impurities into two regions (a drain diffusion region and a source diffusion region). The two regions are separated by a distance of undifrused substrate material called a channel, over which the gate terminal is constructed. By applying a voltage to the gate terminal of the transistor, the channel is energized such that current may flow between the source diffusion region and the drain diffusion region.

A particular CMOS semiconductor technology requires a relatively narrow range of power supply voltages to operate properly. If a power supply voltage lower than the specified range is used, transistors may not be capable of developing voltage levels large enough to cause significant current flow through the transistors. If a power supply voltage higher than the specified range is used, many -problems may occur. Among such problems are "hot carrier effects" which may cause damage to transistors. Carriers are electrons or holes which flow through the channel region of a transistor when it is energized via a voltage difference between the gate terminal and the source terminal of the transistor. Hot carrier effects may be generated in two ways. First, substrate hot carriers are generated as a result of large voltage differences between the gate terminal and the bulk terminal of a transistor. Carriers are generated in the bulk and accelerate across the channel. If the voltage difference is large enough, the carriers may inject into the oxide layer between the gate conductor and the silicon surface. Second, channel hot carriers originate from channel current and impact ionization current near the drain junction. Carriers may gain sufficient energy to inject into the aforementioned oxide. Carriers embedded in the oxide cause the threshold voltage of the transistor to shift, reducing current capability of the transistor. Another problem associated with voltages higher than the specified range is oxide breakdown. When oxide breakdown occurs, an electrical short is created between the gate terminal and the source terminal, the drain terminal, or the channel.

Modem integrated circuits are being fabricated in CMOS semiconductor technologies having power supply voltage ranges lower than previously developed CMOS semiconductor technologies. Voltage ranges are decreasing due to the shrinkage of transistor geometries as CMOS semiconductor technologies improve. Shrinking geometries allow more transistors to be placed within a given area of a semiconductor substrate. Thus, more functionality may be included within a particular area of substrate used to manufacture an integrated circuit. As transistor geometries shrink, the voltage that the transistors are capable of withstanding decreases as well. For example, as the length of the channel and the oxide thickness shrinks then the voltage that may be applied across the gate oxide before inducing hot carrier effects and causing oxide breakdown decreases.

Modern integrated circuits are required to interface to older integrated circuits in many applications. For example, computer systems use a mix of integrated circuits implemented in different semiconductor technologies. Some of these integrated circuits require a nominal power supply voltage of 5.0 volts. Other integrated circuits are fabricated in semiconductor technologies requiring a nominal power supply voltage of 3.3 volts. A "nominal" power supply voltage is the power supply voltage at which the transistors embodied in the particular semiconductor technology provide optimal performance and reliability. Typically, the actual power supply may vary higher or lower than the nominal value by some percentage defined by the semiconductor manufacturer. A 5 % to 10% variation from the nominal value is typically allowed.

A particularly difficult problem with interfacing integrated circuits requiring dissimilar nominal power supply voltages is handling the higher voltages that the 5.0 volt integrated circuits produce on interface buses to which 3.3 volt integrated circuits are connected. Typically, CMOS integrated circuits produce voltages on their output pins which are substantially equal to the power supply voltage if the pin is conveying a logical one value. Therefore, 5.0 volt integrated circuits may drive a 5.0 volt signal onto an interface bus. A 5.0 volt signal connected directly to an integrated circuit with a nominal power supply voltage of 3.3 volts would cause hot carrier effects and/or oxide breakdown to occur in the receiving integrated circuit. It would be advantageous for integrated circuits with a 3.3 volt power supply to be able to receive 5.0 volt input signals and drive 5.0 volt output signals without sustaining damage when interfacing to integrated circuits having 5.0 volt power supplies.

SUMMARY OF THE INVENTION

The problems outlined above are in large part solved by output driver and input receiver circuits in accordance with the present invention. The output driver circuit employs a series-connected pair of PMOS transistors and a series-connected pair of NMOS transistors instead of the typical single PMOS transistor or single NMOS transistor configuration. One of the PMOS transistors and one of the NMOS transistors have their gate terminals connected to a pair of power sources such that these transistors maintain a voltage level on the node connecting the transistor to the corresponding transistor of the transistor pair. The safe voltage level is maintained during times when the series-connected pair of transistors are not conducting current. By maintaining this voltage, the voltage difference between any two terminals of the transistors within the output driver circuit is advantageously held below the maximum allowable voltage of the semiconductor technology in which the transistors are fabricated. The transistors of the output driver circuit are therefore not exposed to undue stress due to hot carrier effects or oxide breakdown, yet are able to drive voltages greater than the maximum allowable voltage of the semiconductor technology in which they are fabricated.

An input receiver circuit is also described which contains an NMOS transistor between the input conductor and receiving inverter circuits. This NMOS transistor has its gate terminal connected to a power supply conveying the same voltage as the power supply for the integrated circuit core. The NMOS transistor limits the voltage at the input of the receiving inverter circuits to no more than the power supply voltage, advantageously shielding the receiving inverter circuits from relatively large voltage levels that may exist external to the integrated circuit.

The present invention contemplates an output driver circuit for producing an output voltage which is larger than a maximum allowable voltage of a semiconductor technology in which the output driver circuit is employed. The output driver circuit comprises a driving transistor, an isolation transistor, and an output conductor. The driving transistor is coupled to a power supply conductor, and the isolation transistor is coupled in series between said driving transistor and the output conductor. The isolation transistor is additionally configured with a bulk connection to its source terminal. Coupled to the gate terminal of the isolation transistor is a reference voltage conductor. The reference voltage conductor is powered, during use, with a reference voltage between the maximum allowable voltage and ground.

The present invention further contemplates an input receiver circuit for receiving an input voltage which is larger than a maximum allowable voltage of a semiconductor technology in which the input receiver circuit is employed. The input receiver circuit comprises an inverter circuit, an isolation transistor, a pullup transistor, and a reference voltage conductor. The isolation transistor is coupled between an input conductor and the inverter circuit: and the reference voltage conductor is coupled to the gate terminal of the isolation transistor. The pullup transistor is coupled between a power supply conductor and .the input to the inverter circuit. During use. the reference voltage conductor is powered with a reference voltage between the maximum allowable voltage and ground.

The present invention still further contemplates an input/output circuit for receiving an input voltage and driving an output voltage which is larger than a maximum allowable voltage of a semiconductor technology in which the input output circuit is employed. The input/output circuit comprises an output driver circuit, an input receiver circuit, and a pair of level translator circuits. Within the driver circuit are a driving transistor coupled to a power supply conductor, an isolation transistor coupled in series between the driving transistor and an output conductor, and a reference voltage conductor coupled to the gate terminal of the isolation transistor. The reference voltage conductor is powered, during use, with a reference voltage between the maximum allowable voltage and ground. Included in the input receiver circuit are an inverter circuit, a second isolation transistor coupled between the output conductor and the inverter circuit, and a second reference voltage conductor coupled to the gate of the second isolation transistor. During use, the second reference voltage conductor is powered with a second reference voltage between the maximum allowable voltage and ground. The level translator circuits are coupled between an integrated circuit core and the output driver circuit. The level translator circuits are configured to translate a voltage level from a first power supply voltage to a second power supply voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

Figure 1 depicts a block diagram of a typical integrated circuit.

Figure 2 is a block diagram of an input/output driver circuit according to the present invention. Figure 3 is a circuit diagram of an exemplary level translator circuit.

Figure 4 is a circuit diagram of an output driver circuit according to the present invention.

Figure 5 is a circuit diagram of an input receiver circuit according to the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

Turning now to Figure 1, a block diagram of a typical integrated circuit 10 is shown. Integrated circuit 10 is divided into a core section 14 and an input output (I/O) section 12. Core section 14 contains circuits which implement the predetermined set of functions which integrated circuit 10 embodies. I/O section 12 contains circuits configured to effect communication between core section 14 and other integrated circuits and electrical devices that integrated circuit 10 may be connected to. Circuits within I/O section 12 include input receiver circuits, output driver circuits, and input/output driver circuits.

Input receiver circuits are configured to receive communicative signals from other integrated circuits and electrical devices. Input receiver circuits serve as a buffer to protect circuits within core section 14 from relatively large voltage levels that may occur at inputs to integrated circuit 10. Also, signals received by receiver circuits tend to have slow rise and fall times associated with them. The term "rise time" refers to an interval of time during which a signal transitions from a low voltage level to a high voltage level. The term "fall time" refers to an interval of time during which a signal transitions from a high voltage level to a low voltage level. Digital circuits operate more efficiently when they receive signal inputs having fast rise and fall times, and so the input receiver circuits convert the slow rise and fall time input signals to a fast rise and fall time signal suitable for circuits within core section 14.

Output driver circuits are configured to "drive" (i.e. transfer) communicative signals from core section 14 to integrated circuits and electrical devices connected to integrated circuit 10. Output driver circuits provide the relatively large amount of current necessary to charge the relatively large capacitances associated with external connections between electrical devices. Therefore, transistors within core section 14 need not be capable of relatively high current levels and may instead be configured to drive the relatively smaller capacitances associated with internal connections of integrated circuit 10. Output driver circuits also serve to buffer circuits within core section 14 from external voltages and currents, similar to receiver circuits. Input/output driver circuits are configured to both drive and receive communicative signals from core section 14 to integrated circuits and electrical devices connected to integrated circuit 10. Circuits within core section 14 and other integrated circuits and electrical devices utilize a predetermined protocol for determining when a device may drive communicative signals which operate as both input and output signals. The predetermined protocol guarantees that no two integrated circuits or electrical devices drive a particular input/output signal simultaneously.

Turning now to Figure 2. a block diagram of an input output driver circuit 20 used in I/O section 12 of integrated circuit 10 is shown. Input output driver circuit 20 contains a first level translator circuit 22, a second level translator circuit 24, an output driver circuit 26, an input receiver circuit 28, and a combinatorial circuit 30. Input/output driver circuit 20 may be modified to create an input receiver circuit by removing all elements except for input receiver circuit 28. Input output driver circuit 20 may be modified to create an output driver circuit by removing input receiver circuit 28.

First level translator circuit 22 is configured with two power conductors. A first power conductor 32 is coupled to a power source (VCC) which supplies power during use to core section 14 of integrated circuit 10. In one embodiment, VCC is 3.3 volts. A second power conductor 34 is coupled to another power source which supplies a reference voltage (Vref) during use. In one embodiment. Vref is 1.7 volts.

First level translator circuit 22 is designed to translate a pair of signals on an input bus 36 which conveys voltages between ground and VCC into a pair of signals on intermediate bus 38 which conveys voltages between Vref and VCC. The translation is effected such that a ground voltage on input bus 36 is converted into a Vref voltage on intermediate bus 38, and such that a VCC voltage on input bus 36 is converted into a VCC voltage on intermediate bus 38. Voltages between VCC and ground on input bus 36 are converted to voltages between VCC and Vref on intermediate bus 38.

Second level translator circuit 24 is similarly coupled to a pair of power supply conductors. A third power supply conductor 40 is coupled to a third power source which supplies a voltage Vout during use. Vout is the output voltage that output driver circuit 26 produces when driving a high value onto an output pin. In one embodiment, Vout is 5.0 volts. Second level translator circuit 24 is also coupled to second power conductor 34, intermediate bus 38, and a first driver input conductor 42.

Second level translator circuit 24 is configured to translate a voltage on intermediate bus 38 (which conveys voltages between VCC and Vref, as described above) to a corresponding voltage on first driver input conductor 42 between Vout and Vref. A voltage of Vref on intermediate bus 38 is converted to a voltage of Vref on first driver input conductor 42. A voltage of VCC on intermediate bus 38 is converted to a voltage of Vout on first driver input conductor 42. Voltages between VCC and Vref on intermediate bus 38 are converted to corresponding voltages between Vout and Vref on first driver input conductor 42. In one embodiment, input bus 36 and intermediate bus 38 each consist of a pair of conductors upon which a single logical value and its logically inverted value are conveyed. In other words, when a relatively high voltage is conveyed on one of the pair of conductors, a relatively low voltage is conveyed on the other of the pair of conductors.

Combinatorial circuit 30 is configured to generate voltages on input bus 36 and a second voltage on a second driver input conductor 48 dependent on the values of a signal on a data conductor 44 and a signal on an enable conductor 46. Data conductor 44 and enable conductor 46 are coupled to circuits within core section 14 (not shown). Data conductor 44 conveys a value which core section 14 requires to communicate to another electrical device connected to integrated circuit 10. Enable conductor 46 conveys a value which indicates whether or not the value on data conductor 44 should be communicated. In one embodiment, a logical zero (represented by a ground voltage) on enable conductor 46 indicates the value on data conductor 44 should be communicated, and a logical one (represented by a VCC voltage) on enable conductor 46 indicates the value on data conductor 44 should not be communicated. In one embodiment, a logical zero is conveyed on the non-inverted conductor of input bus 36 if data conductor 44 conveys a logical one and enable conductor 46 conveys a logical zero, and a logical one is conveyed for other combinations of values on data conductor 44 and enable conductor 46. Additionally, a logical one is conveyed on second driver input conductor 48 if both data conductor 44 and enable conductor 46 convey a logical zero, and a logical zero is conveyed on second driver input conductor 48 for other combinations of values on data conductor 44 and enable conductor 46.

Output driver circuit 26 is configured to produce an output signal between Vout and ground on input/output conductor 50. Output driver circuit 26 produces a voltage of Vout when a voltage of Vref is conveyed on first driver input conductor 42, and a ground voltage level when a voltage of VCC is conveyed on second driver input conductor 48. Output driver circuit 26 will be described in more detail below with respect to Figure 4. Input receiver circuit 28 is coupled between input/output conductor 50 and a received input conductor 52. Input receiver circuit 28 receives voltages between ground and Vout on input/output conductor 50 and produces a signal on received input conductor 52 corresponding to the voltage received on input/output conductor 50. Particularly, a voltage of Vout on input/output conductor 50 results in a voltage of VCC on received input conductor 52. A ground voltage level on input/output conductor 50 results in a ground voltage level on received input conductor 52. Received input conductor 52 is coupled to circuits within core section 14 (not shown) which interpret the voltages conveyed on received input conductor 52.

Turning now to Figure 3, an embodiment of a level translator circuit 60 that may be used as first level translator circuit 22 or second level translator circuit 24 is shown. Level translator circuit 60 is configured with an input conductor 62, an inverted input conductor 64, an output conductor 66, and an inverted output conductor 68. Level translator circuit 60 consists of six transistors 70, 72, 74, 76, 78, and 80. Transistors 70, 72, 78, and 80 are NMOS transistors, while transistors 74 and 76 are PMOS transistors. Two power conductors are provided for level translator circuit 60: a Vhigh power conductor 82 and a Vlow power conductor 84. Vhigh power conductor 82 is powered to a Vhigh voltage during use, while Vlow power conductor 84 is powered to a Vlow voltage during use.

Generally speaking, level translator circuit 60 translates a voltage on input conductor 62 to a corresponding voltage on output conductor 66. The voltages conveyed on output conductor 66 range between the Vlow voltage level and the Vhigh voltage level. Vhigh is a voltage level which is greater than or equal to the highest voltage that is conveyed on input conductor 62 or inverted input conductor 64.

Transistor 70 has its gate terminal coupled to input conductor 62, and discharges inverted output conductor 68 to the Vlow voltage level during times when a voltage level on input conductor 62 is greater than Vlow by at least one threshold voltage value. Similarly, fransistor 72 has its gate terminal coupled to inverted input conductor 64 and discharges output conductor 66 to the Vlow voltage, level during times when a voltage level on inverted input conductor 64 is greater than Vlow by at least one threshold voltage value. Transistor 74 has its gate terminal coupled to inverted output conductor 68 and charges output conductor 66 to the Vhigh voltage level during times when a voltage on inverted output conductor 68 is less than Vhigh by at least one threshold voltage value. Similarly, transistor 76 has its gate terminal coupled to output conductor 66 and charges inverted output conductor 68 to the Vhigh voltage level during times when a voltage on output conductor 66 is less than Vhigh by at least one threshold voltage value.

Together, transistors 70, 72, 74, and 76 provide the translation function from input conductor 62 to output conductor 66 and from inverted input conductor 64 to inverted output conductor 68. Transistors 78 and 80 are provided to speed up the translation of a voltage from an input conductor to a corresponding output conductor. During times of signal transition, transistors 74 and 72 or transistors 70 and 76 may be charging the respective conductor 66 or 68 simultaneously. Since the transistors are charging to dissimilar voltage levels, a conflict exists between the transistors. Transistors 78 and 80 are provided to aid transistors 76 and 74, respectiveh . during times of signal transition. Transistor 78 aids transistor 76 in driving inverted output conductor 68 high during times when inverted input conductor 64 is at a high voltage. The charging action of transistors 78 and 76 is greater than the discharging action of transistor 70, and inverted output conductor 68 charges more quickly toward Vhigh. Transistor 80 is configured to aid transistor 74 in a similar fashion during times when input conductor 62 is at a high voltage.

The function of level translator 60 will be further illuminated with an example. In the example, input conductor 62 transitions to a relatively high voltage and inverted input conductor 64 transitions to a relatively low voltage. Because input conductor 62 is conveying a voltage greater than Vlow, current begins to flow through transistors 70 and 80. Because inverted input conductor 64 is conveying a relatively low voltage, no electric current flows through transistors 72 and 78. Transistor 70 begins discharging inverted output conductor 68 toward the Vlow voltage level, and transistor 80 begins charging output conductor 66. As the voltage on inverted output conductor 68 decreases, current begins to flow through transistor 74. Transistor 74 continues charging output conductor 66 to a Vhigh voltage level. Output conductor 66 therefore conveys a Vhigh voltage level when input conductor 62 conveys a relatively high voltage level. Also, as the voltage on output conductor 66 rises to the Vhigh level, the current flow through transistor 76 reduces and substantially stops. Therefore, transistor 70 is able to discharge inverted output conductor 68 to the Vlow voltage level. As will be appreciated by those skilled in the art, a relatively low voltage on input conductor 62 and relatively high voltage on inverted input conductor 64 similarly results in a Vlow voltage on output conductor 66 and a Vhigh voltage on inverted output conductor 68.

In one embodiment of input/output driver circuit 20 (shown in Figure 2). level translator circuit 60 is used as first level translator circuit 22 or as second level translator circuit 24. When used as first level franslator circuit 22, input bus 36 represents input conductor 62 and inverted input conductor 64. Also. output conductor 66 and inverted output conductor 68 are indicative of intermediate bus 38. First power conductor 32 is power conductor 82. and second power conductor 34 is power conductor 84. When level translator circuit 60 is used as second level translator circuit 24, intermediate bus 38 is input conductor 62 and inverted input conductor 64. Also, output conductor 66 is first driver input conductor 42. Third power conductor 40 is power conductor 82, and second power conductor 34 is power conductor 84.

In another embodiment of input output driver circuit 20, a pair of series-connected inverters are used for first level translator circuit 22, and level translator circuit 60 is used as second level translator circuit 24. The pair of series connected inverters are powered by first power conductor 32 and second power conductor 34 in this embodiment.

Turning now to Figure 4, a circuit diagram of output driver circuit 26 (as shown in block form in Figure 2) is depicted. Output driver circuit 26 is configured with a series-connected pair of PMOS transistors 100 and 102 coupled between third power supply conductor 40 and input/output conductor 50. Coupled between input/output conductor 50 and a ground conductor 104 is a pair of series-connected NMOS transistors 106 and 108. PMOS transistor 100 has a gate terminal connected to first driver input conductor 42, and PMOS transistor 102 has a gate terminal connected to second power supply conductor 34. The gate terminal of NMOS transistor 106 is connected to first power supply conductor 32. while the gate terminal of NMOS transistor 108 is connected to second driver input conductor 48.

Also depicted in Figure 4 are the bulk connections of PMOS transistors 100 and 102 and NMOS transistors 106 and 108. Bulk connection of PMOS transistor 100 to second power supply conductor 40 and bulk connections of NMOS transistors 106 and 108 to ground conductor 104 are the standard bulk connections for PMOS transistor and NMOS transistor transistors in an N-well CMOS technology, respectively. However, PMOS fransistor 102 has a bulk connection to a node 112 between PMOS fransistor 100 and PMOS transistor 102. This connection removes the capacitance which normally exists between the source terminal of PMOS transistor 102 and the bulk. In this manner, the capacitance on node 112 is decreased and so switching speed is increased with respect to node 112.

Generally speaking, the driver circuit of Figure 4 is configured to drive input/output conductor 50 to the Vout voltage provided on third power supply conductor 40 and to the ground voltage level provided on ground conductor 104. In order to prevent hot carrier effects and oxide breakdown from occurring, it is necessary to limit the difference in voltage across any two terminals of transistors 100, 102, 106, and 108 to a maximum allowable voltage defined by the semiconductor technology in which the transistors are fabricated. By providing PMOS transistor 102 and NMOS transistor 106 and connecting their gate terminals as shown, this voltage limitation is provided. In one embodiment, the above mentioned maximum allowable voltage is 3.9 volts.

NMOS fransistor 106 provides the voltage limitation by holding a node 1 10 substantially near (i.e. a threshold voltage value less than) the core supply voltage, represented as VCC, during times when second input conductor 48 conveys a ground voltage. If NMOS transistor 106 were not provided, then NMOS transistor 108 would be connected directly to input/output conductor 50. During times that input/output conductor 50 is conveying a Vout voltage (such as when PMOS transistors 100 and -102 have charged input/output conductor 50), the voltage across the source and drain terminals of NMOS transistor 108 would be Vout (since NMOS transistor 108 is connected to ground conductor 104). Since Vout may be larger than the maximum allowable voltage for the semiconductor fabrication process. NMOS transistor 108 would suffer from hot carrier effects and/or oxide breakdown. However, NMOS transistor 106 is provided. During times when NMOS transistor 108 is not conducting current, the voltage on node 1 10 cannot rise above VCC. The voltage on node 110 is limited in this manner due to the threshold voltage of NMOS transistor 106. If the voltage on input/output conductor 50 rises above VCC (for example, to the Vout voltage) and the voltage on node 110 is below VCC, then NMOS fransistor 106 conducts current because the voltage on the gate terminal of NMOS transistor 106 is larger than the voltage on its source terminal. As the voltage on node 110 rises to within a threshold voltage of VCC, then NMOS transistor 106 substantially stops conducting current. When NMOS fransistor 108 is activated via a VCC voltage level on second driver input conductor 48, NMOS fransistor 108 drains the voltage from node 110. NMOS transistor 106 begins drawing current from output conductor 50, until output conductor 50 is lowered to the ground voltage level. If output conductor 50 is conveying a Vout voltage level when NMOS transistor 108 is activated, then NMOS transistor 106 may temporarily endure a voltage larger than the maximum allowable voltage. However, this time period is relatively short and so the hot carrier effects which might occur are negligible. Therefore, neither NMOS fransistor 106 nor NMOS transistor 108 is significantly degraded due to hot carrier effects or oxide breakdown while existing in an environment containing voltages larger than the maximum allowable voltage associated with the semiconductor fabrication process used to create NMOS transistor 106 and NMOS transistor 108.

PMOS transistor 100 and PMOS transistor 102 operate similarly to NMOS transistor 108 and NMOS fransistor 106, respectively. However, the gate of PMOS transistor 102 is held at a Vref voltage as opposed to the VCC voltage, and node 112 does not fall lower than Vref plus one threshold voltage value.

Turning now to Figure 5, a circuit diagram of input receiver circuit 28 is shown. Receiver circuit 28 is coupled to input/output conductor 50 and to received input conductor 52, as well as to first power supply conductor 32 and ground conductor 104. NMOS transistor 120 is coupled between input/output conductor 50 and the gate terminals of transistors 122 and 124. Transistors 122 and 124 are configured as an inverter circuit. The gate terminal of NMOS transistor 120 is coupled to first power supply conductor 32, similar to NMOS transistor 106 in output driver circuit 26 (shown in Figure 4). Similar to NMOS transistor 106, NMOS transistor 120 limits the voltage conveyed on node 126 to no more than VCC minus one threshold voltage value. Therefore, transistors 122 and 124 are shielded from the Vout voltage level that may be driven on input/output conductor 50. A Vout-tolerant input receiver circuit is thereby formed in a semiconductor technology in which Vout is larger than the maximum allowable voltage of the semiconductor technology.

It is noted that the voltage level on node 126 will not rise completely to the VCC voltage level under the current provided by NMOS transistor 120. NMOS transistor 120 is only capable of charging node 126 to a threshold voltage below VCC. In order to ensure that node 126 rises completely to VCC when output conductor 50 conveys a Vout voltage, input receiver 28 includes PMOS transistor 128. The gate of PMOS transistor 128 is coupled to the output node of the inverter circuit formed by transistors 122 and 124. When the inverter circuit begins switching its output node to a logical zero, then voltage on the gate of PMOS fransistor 128 drops below VCC and PMOS transistor 128 begins conducting current. Node 126 is thereby charged fully to the VCC voltage level.

Input receiver circuit 28 further includes a second inverter circuit connected to the inverter circuit formed by transistors 122 and 124. The second inverter circuit is formed by transistors 130 and 132.

Received input conductor 52 is coupled to the output node of the second inverter circuit. By passing the voltage conveyed on output conductor 50 through two inverter circuits, a signal containing a logic level which is non-inverted from the logic level on input/output conductor 50 is conveyed on received input conductor 52.

In accordance with the above disclosure an input output driver circuit, input receiver circuit, and output driver circuit have been described which are capable of driving and receiving voltages which are larger than the maximum allowable voltage of the semiconductor process in which the circuits are fabricated. These circuits may be incorporated into an integrated circuit, allowing the integrated circuit to be advantageously coupled to other electrical devices which utilize voltages larger than the maximum allowable voltage of the integrated circuit. Such an integrated circuit may be incorporated into devices which utilize other integrated circuits manufactured in semiconductor technologies requiring dissimilar supply voltages without damage occurring to any of the integrated circuits.

Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

WHAT IS CLAIMED IS:

1. An output driver circuit for producing an output voltage which is larger than a maximum allowable voltage of a semiconductor technology in which said output driver circuit is employed, comprising:

a driving transistor coupled to a power supply conductor:

an isolation transistor coupled in series between said driving transistor and an output conductor wherein said isolation transistor is configured with a bulk terminal connected to a source terminal of said isolation transistor; and

a reference voltage conductor coupled to a gate terminal of said isolation transistor wherein said reference voltage conductor is powered, during use, with a reference voltage between said maximum allowable voltage and a ground voltage.

2. The output driver circuit as recited in claim 1 wherein said driving transistor and said isolation transistor are PMOS transistors.

3. The output driver circuit as recited in claim 1 wherein said power supply conductor is powered, during use, with said output voltage.

4. The output driver circuit as recited in claim 1 wherein said reference voltage is nominally 1.7 volts.

5. The output driver circuit as recited in claim 1 wherein said output voltage level is nominally 5.0 volts.

6. The output driver circuit as recited in claim 1 further comprising:

a second driving transistor coupled to a second power supply conductor;

a second isolation transistor coupled in series between said second driving transistor and said output conductor; and

a second reference voltage conductor coupled to a gate terminal of said second isolation transistor wherein said second reference voltage conductor is powered, during use, with a second reference voltage between said maximum allowable voltage and ground.

7. The output driver circuit as recited in claim 6 wherein said second driving transistor and said second isolation transistor are NMOS transistors.

8. The output driver circuit as recited in claim 6 wherein said second power supply conductor is powered, during use. with said ground voltage.

9. The output driver circuit as recited in claim 6 wherein said second reference voltage level is nominally 3.3 volts.

10. An input receiver circuit for receiving an input voltage which is larger than a maximum allowable voltage of a semiconductor technology in which said input receiver circuit is employed, comprising:

an inverter circuit;

an isolation fransistor coupled between an input conductor and said inverter circuit;

a pullup transistor coupled between a power supply conductor and said isolation transistor wherein a gate terminal of said pullup fransistor is coupled to an output terminal of said inverter circuit; and

11. The input receiver circuit as recited in claim 10 wherein said isolation transistor is an NMOS fransistor.

12. The input receiver circuit as recited in claim 10 wherein said reference voltage is nominally 3.3 volts.

13. The input receiver circuit as recited in claim 10 wherein said pullup transistor is configured to charge a node between said pullup fransistor and said isolation transistor to a power supply voltage presented by said power supply conductor during a time in which said output terminal of said inverter is producing a ground voltage.

14. The input receiver circuit as recited in claim 10 wherein said power supply conductor is powered, during use. to a nominal voltage level of 3.3 volts.

15. The input receiver circuit as recited in claim 10 further comprising a second inverter circuit coupled to said first inverter circuit in series such that said input receiver circuit forms a non-inverting input receiver circuit.

16. An input/output circuit for receiving an input voltage and driving an output voltage which is larger than a maximum allowable voltage of a semiconductor technology in which said input/output circuit is employed, comprising:

an output driver circuit including:

a driving transistor coupled to a power supply conductor; an isolation transistor coupled in series between said driving transistor and an output conductor; and

a reference voltage conductor coupled to a gate terminal of said isolation transistor wherein said reference voltage conductor is powered, during use, with a reference voltage between said maximum allowable voltage and a ground voltage:

an input receiver circuit including:

an inverter circuit;

a second isolation transistor coupled between said output conductor and said inverter circuit;

a pullup fransistor coupled between said power supply conductor and said second isolation fransistor wherein a gate terminal of said pullup transistor is coupled to an output terminal of said inverter circuit; and

a second reference voltage conductor coupled to a gate terminal of said second isolation transistor wherein said second reference voltage conductor is powered, during ' use, with a second reference voltage between said maximum allowable voltage and said ground voltage; and

a pair of level translator circuits coupled between an integrated circuit core and said output driver circuit wherein said pair of level translator circuits is configured to translate a voltage level from a first power supply voltage to a second power supply voltage.

17. The input/output circuit as recited in claim 16 wherein a first of said pair level translator circuits comprises a first level franslator circuit including a pair of inverter circuits coupled in series, wherein said power supply source is powered, during use. to said first power supply voltage and wherein a ground source coupled to said inverter circuits is powered, during use, to a third reference voltage.

18. The input/output circuit as recited in claim 16 wherein said first power supply voltage is nominally 3.3 volts.

19. The input output circuit as recited in claim 16 wherein said reference voltage is nominally 1.7 volts.

20. The input/output circuit as recited in claim 17 wherein a second of said pair of level translator circuits further comprises a second level translator circuit configured to translate an output voltage of said first level translator circuit to a voltage between said reference voltage and said second power supply voltage.

21. The input output circuit as recited in claim 16 wherein said second power supply voltage is nominally 5.0 volts.