DE69125875T2 - Nichtflüchtige Halbleiterspeicheranordnung - Google Patents

Nichtflüchtige Halbleiterspeicheranordnung

Info

Publication number
DE69125875T2
DE69125875T2 DE69125875T DE69125875T DE69125875T2 DE 69125875 T2 DE69125875 T2 DE 69125875T2 DE 69125875 T DE69125875 T DE 69125875T DE 69125875 T DE69125875 T DE 69125875T DE 69125875 T2 DE69125875 T2 DE 69125875T2
Authority
DE
Germany
Prior art keywords
potential
memory device
semiconductor memory
memory cells
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69125875T
Other languages
English (en)
Other versions
DE69125875D1 (de
Inventor
Masashi Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69125875D1 publication Critical patent/DE69125875D1/de
Application granted granted Critical
Publication of DE69125875T2 publication Critical patent/DE69125875T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE69125875T 1990-02-23 1991-02-22 Nichtflüchtige Halbleiterspeicheranordnung Expired - Fee Related DE69125875T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2040911A JP2504599B2 (ja) 1990-02-23 1990-02-23 不揮発性半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69125875D1 DE69125875D1 (de) 1997-06-05
DE69125875T2 true DE69125875T2 (de) 1997-09-25

Family

ID=12593689

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69125875T Expired - Fee Related DE69125875T2 (de) 1990-02-23 1991-02-22 Nichtflüchtige Halbleiterspeicheranordnung

Country Status (5)

Country Link
US (1) US5262985A (de)
EP (1) EP0443610B1 (de)
JP (1) JP2504599B2 (de)
KR (1) KR940005899B1 (de)
DE (1) DE69125875T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930007527B1 (ko) * 1990-09-22 1993-08-12 삼성전자 주식회사 스토리지 셀 어레이와 주변회로를 갖는 불휘발성 반도체 메모리 장치의 제조방법 및 그 구조
JP2799530B2 (ja) * 1991-11-16 1998-09-17 三菱電機株式会社 半導体記憶装置の製造方法
DE69227011T2 (de) * 1991-11-20 1999-02-18 Fujitsu Ltd Löschbare Halbleiterspeicheranordnung mit verbesserter Zuverlässigkeit
DE69227020T2 (de) * 1992-03-11 1999-02-18 St Microelectronics Srl Dekodierschaltung fähig zur Ubertragung von positiven und negativen Spannungen
US5411908A (en) * 1992-05-28 1995-05-02 Texas Instruments Incorporated Flash EEPROM array with P-tank insulated from substrate by deep N-tank
WO1994014196A1 (en) * 1992-12-08 1994-06-23 National Semiconductor Corporation High density contactless flash eprom array using channel erase
JPH07161845A (ja) * 1993-12-02 1995-06-23 Nec Corp 半導体不揮発性記憶装置
US5432749A (en) * 1994-04-26 1995-07-11 National Semiconductor Corporation Non-volatile memory cell having hole confinement layer for reducing band-to-band tunneling
US5687118A (en) * 1995-11-14 1997-11-11 Programmable Microelectronics Corporation PMOS memory cell with hot electron injection programming and tunnelling erasing
US5867425A (en) * 1997-04-11 1999-02-02 Wong; Ting-Wah Nonvolatile memory capable of using substrate hot electron injection
US5896315A (en) * 1997-04-11 1999-04-20 Programmable Silicon Solutions Nonvolatile memory
JP4427108B2 (ja) * 1998-03-27 2010-03-03 株式会社東芝 半導体装置及びその製造方法
JP2000311992A (ja) 1999-04-26 2000-11-07 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US6831325B2 (en) * 2002-12-20 2004-12-14 Atmel Corporation Multi-level memory cell with lateral floating spacers
KR20050009104A (ko) * 2003-07-15 2005-01-24 현대자동차주식회사 파워스티어링 펌프의 결합구조
US8099783B2 (en) * 2005-05-06 2012-01-17 Atmel Corporation Security method for data protection

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2645585B2 (ja) * 1989-03-10 1997-08-25 工業技術院長 半導体不揮発性メモリ及びその書き込み方法
JPS62183161A (ja) * 1986-02-07 1987-08-11 Hitachi Ltd 半導体集積回路装置
JPS6352478A (ja) * 1986-08-22 1988-03-05 Hitachi Ltd 半導体集積回路装置
JPS63211767A (ja) * 1987-02-27 1988-09-02 Toshiba Corp 半導体記憶装置
JPH0814991B2 (ja) * 1988-01-28 1996-02-14 株式会社東芝 電気的消去可能不揮発性半導体記憶装置
US5075890A (en) * 1989-05-02 1991-12-24 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with nand cell
US5029139A (en) * 1989-07-19 1991-07-02 Texas Instruments Incorporated Word erasable buried bit line EEPROM
US5126808A (en) * 1989-10-23 1992-06-30 Advanced Micro Devices, Inc. Flash EEPROM array with paged erase architecture
US5132935A (en) * 1990-04-16 1992-07-21 Ashmore Jr Benjamin H Erasure of eeprom memory arrays to prevent over-erased cells
US5138576A (en) * 1991-11-06 1992-08-11 Altera Corporation Method and apparatus for erasing an array of electrically erasable EPROM cells

Also Published As

Publication number Publication date
KR920000137A (ko) 1992-01-10
DE69125875D1 (de) 1997-06-05
JP2504599B2 (ja) 1996-06-05
EP0443610B1 (de) 1997-05-02
JPH03245566A (ja) 1991-11-01
US5262985A (en) 1993-11-16
EP0443610A3 (en) 1994-10-05
EP0443610A2 (de) 1991-08-28
KR940005899B1 (ko) 1994-06-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee