DE69119208T2 - Halbleiter-Speichereinrichtung mit Möglichkeit zum direkten Einlesen des Potentials von Bit-Lines - Google Patents
Halbleiter-Speichereinrichtung mit Möglichkeit zum direkten Einlesen des Potentials von Bit-LinesInfo
- Publication number
- DE69119208T2 DE69119208T2 DE69119208T DE69119208T DE69119208T2 DE 69119208 T2 DE69119208 T2 DE 69119208T2 DE 69119208 T DE69119208 T DE 69119208T DE 69119208 T DE69119208 T DE 69119208T DE 69119208 T2 DE69119208 T2 DE 69119208T2
- Authority
- DE
- Germany
- Prior art keywords
- possibility
- potential
- memory device
- semiconductor memory
- bit lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2402458A JP2685357B2 (ja) | 1990-12-14 | 1990-12-14 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69119208D1 DE69119208D1 (de) | 1996-06-05 |
DE69119208T2 true DE69119208T2 (de) | 1996-10-02 |
Family
ID=18512279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69119208T Expired - Fee Related DE69119208T2 (de) | 1990-12-14 | 1991-12-11 | Halbleiter-Speichereinrichtung mit Möglichkeit zum direkten Einlesen des Potentials von Bit-Lines |
Country Status (5)
Country | Link |
---|---|
US (1) | US5233558A (de) |
EP (1) | EP0490363B1 (de) |
JP (1) | JP2685357B2 (de) |
KR (1) | KR950002294B1 (de) |
DE (1) | DE69119208T2 (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2668165B2 (ja) * | 1990-12-06 | 1997-10-27 | 三菱電機株式会社 | 半導体記憶装置 |
EP0579862A1 (de) * | 1992-07-24 | 1994-01-26 | Siemens Aktiengesellschaft | Integrierte Halbleiterspeicheranordnung |
JP2894115B2 (ja) * | 1992-11-10 | 1999-05-24 | 松下電器産業株式会社 | カラム選択回路 |
US5377143A (en) * | 1993-03-31 | 1994-12-27 | Sgs-Thomson Microelectronics, Inc. | Multiplexing sense amplifier having level shifter circuits |
US5487048A (en) * | 1993-03-31 | 1996-01-23 | Sgs-Thomson Microelectronics, Inc. | Multiplexing sense amplifier |
JPH07130185A (ja) * | 1993-09-13 | 1995-05-19 | Mitsubishi Electric Corp | 半導体メモリ装置 |
US5544101A (en) * | 1994-03-28 | 1996-08-06 | Texas Instruments Inc. | Memory device having a latching multiplexer and a multiplexer block therefor |
JP2776327B2 (ja) * | 1995-08-31 | 1998-07-16 | 日本電気株式会社 | データ転送装置 |
KR0157904B1 (ko) * | 1995-10-18 | 1999-02-01 | 문정환 | 메모리의 센스 증폭회로 |
US5680365A (en) * | 1996-05-16 | 1997-10-21 | Mitsubishi Semiconductor America, Inc. | Shared dram I/O databus for high speed operation |
JP3255017B2 (ja) * | 1996-05-24 | 2002-02-12 | 日本電気株式会社 | 半導体記憶装置 |
JPH10162577A (ja) * | 1996-12-02 | 1998-06-19 | Toshiba Corp | 半導体記憶装置及びデータ書き込み方法 |
JP2000132969A (ja) | 1998-10-28 | 2000-05-12 | Nec Corp | ダイナミックメモリ装置 |
KR100297324B1 (ko) * | 1998-12-16 | 2001-08-07 | 김영환 | 반도체 집적회로의 증폭기 |
US7184290B1 (en) | 2000-06-28 | 2007-02-27 | Marvell International Ltd. | Logic process DRAM |
AU2000268134A1 (en) * | 2000-07-07 | 2002-01-21 | Mosaid Technologies Incorporated | A method and apparatus for accelerating signal equalization between a pair of signal lines |
JP4437891B2 (ja) * | 2003-03-24 | 2010-03-24 | Okiセミコンダクタ株式会社 | 同期型dramのデータ書込方法 |
KR100699875B1 (ko) * | 2005-11-08 | 2007-03-28 | 삼성전자주식회사 | 센스앰프 구조를 개선한 반도체 메모리 장치 |
US7477551B2 (en) * | 2006-11-08 | 2009-01-13 | Texas Instruments Incorporated | Systems and methods for reading data from a memory array |
JP5182859B2 (ja) * | 2007-01-29 | 2013-04-17 | 株式会社ステップテクニカ | 評価装置及び評価システム |
JP2014096191A (ja) | 2012-11-09 | 2014-05-22 | Renesas Electronics Corp | 半導体記憶装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4584672A (en) * | 1984-02-22 | 1986-04-22 | Intel Corporation | CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge |
JPS61292292A (ja) * | 1985-06-19 | 1986-12-23 | Toshiba Corp | 半導体記憶装置 |
JPS6192495A (ja) * | 1984-10-11 | 1986-05-10 | Nippon Telegr & Teleph Corp <Ntt> | 半導体記憶装置 |
JPH0664907B2 (ja) * | 1985-06-26 | 1994-08-22 | 株式会社日立製作所 | ダイナミツク型ram |
JPS62157398A (ja) * | 1985-12-28 | 1987-07-13 | Toshiba Corp | 半導体記憶装置 |
JP2659949B2 (ja) * | 1987-03-12 | 1997-09-30 | 株式会社東芝 | ダイナミツク型半導体記憶装置 |
JPS6386191A (ja) * | 1986-09-30 | 1988-04-16 | Toshiba Corp | ダイナミツクメモリ |
KR890003373B1 (ko) * | 1986-11-30 | 1989-09-19 | 삼성전자 주식회사 | 씨모오스 반도체 메모리 장치의 입출력 회로 |
JPH0823994B2 (ja) * | 1986-12-17 | 1996-03-06 | 株式会社日立製作所 | ダイナミツク型ram |
JPH07105137B2 (ja) * | 1987-11-17 | 1995-11-13 | 日本電気株式会社 | 半導体メモリ |
JPH0787035B2 (ja) * | 1988-01-20 | 1995-09-20 | 三菱電機株式会社 | 半導体記億装置 |
US4954992A (en) * | 1987-12-24 | 1990-09-04 | Mitsubishi Denki Kabushiki Kaisha | Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor |
JP2523736B2 (ja) * | 1987-12-24 | 1996-08-14 | 三菱電機株式会社 | 半導体記憶装置 |
JPH0713857B2 (ja) * | 1988-06-27 | 1995-02-15 | 三菱電機株式会社 | 半導体記憶装置 |
JPH0736163B2 (ja) * | 1988-08-26 | 1995-04-19 | 株式会社東芝 | 塗潰しパターン発生装置 |
JPH02156497A (ja) * | 1988-12-07 | 1990-06-15 | Mitsubishi Electric Corp | 半導体記憶装置 |
-
1990
- 1990-12-14 JP JP2402458A patent/JP2685357B2/ja not_active Expired - Fee Related
-
1991
- 1991-12-11 DE DE69119208T patent/DE69119208T2/de not_active Expired - Fee Related
- 1991-12-11 EP EP91121258A patent/EP0490363B1/de not_active Expired - Lifetime
- 1991-12-12 US US07/805,965 patent/US5233558A/en not_active Expired - Lifetime
- 1991-12-13 KR KR1019910022879A patent/KR950002294B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69119208D1 (de) | 1996-06-05 |
JP2685357B2 (ja) | 1997-12-03 |
JPH04216394A (ja) | 1992-08-06 |
EP0490363A1 (de) | 1992-06-17 |
KR920013448A (ko) | 1992-07-29 |
EP0490363B1 (de) | 1996-05-01 |
US5233558A (en) | 1993-08-03 |
KR950002294B1 (ko) | 1995-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69119208T2 (de) | Halbleiter-Speichereinrichtung mit Möglichkeit zum direkten Einlesen des Potentials von Bit-Lines | |
DE3855736D1 (de) | Nichtflüchtige Halbleiter-Speicheranordnung | |
KR900012364A (ko) | 더미비트선을 갖춘 반도체 메모리장치 | |
DE69130993D1 (de) | Nichtflüchtige Halbleiterspeicheranordnung | |
DE69326370D1 (de) | Nichtflüchtige Halbleiterspeicheranordnung | |
DE69133097D1 (de) | Nichtflüchtiger Halbleiterspeicher | |
DE3786819T2 (de) | Nichtflüchtige Halbleiterspeicheranordnung. | |
DE69119277T2 (de) | Nichtflüchtiger Halbleiterspeicher | |
DE3584362D1 (de) | Nichtfluechtige halbleiterspeicheranordnung mit schreibeschaltung. | |
DE69230750D1 (de) | Nichtflüchtige Halbleiterspeicheranordnung | |
DE69120448D1 (de) | Halbleiterspeicheranordnungen von dynamischem Typus | |
DE69125692T2 (de) | Nichtflüchtiger Halbleiter-Speicher | |
DE69228399D1 (de) | Speicherzellenmatrix der Multiporthalbleiterspeicheranordnungstype | |
DE3851416D1 (de) | Statische Direktzugriffshalbleiterspeicheranordnung. | |
DE3853038T2 (de) | Nichtflüchtige Halbleiterspeicheranordnung. | |
DE69120447T2 (de) | Halbleiterspeicheranordnung von dynamischem Typus | |
DE3886284T2 (de) | Halbleiterspeicheranordnung mit nichtflüchtigen Speichertransistoren. | |
DE69123814D1 (de) | Nichtflüchtige Halbleiterspeicheranordnung | |
DE3884820T2 (de) | Nichtflüchtige Halbleiterspeichereinrichtung. | |
DE3784600T2 (de) | Halbleiterspeicher mit schreibfunktion. | |
DE69132436D1 (de) | Halbleiterspeicher mit spaltendekodiertem Bitleitungsausgleich | |
DE3587615D1 (de) | Nichtflüchtige Halbleiterspeicheranordnung. | |
DE68916855D1 (de) | Nichtflüchtige Halbleiterspeicheranordnung. | |
DE3766393D1 (de) | Datenleseschaltung zum gebrauch in halbleiterspeichereinrichtungen. | |
DE3886568D1 (de) | Halbleiter-Speichereinrichtung mit Adressgenerator. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) | ||
8339 | Ceased/non-payment of the annual fee |