DE3785133T2 - Halbleiterspeicheranordnung mit verbesserter bitzeilenordnung. - Google Patents
Halbleiterspeicheranordnung mit verbesserter bitzeilenordnung.Info
- Publication number
- DE3785133T2 DE3785133T2 DE8787115418T DE3785133T DE3785133T2 DE 3785133 T2 DE3785133 T2 DE 3785133T2 DE 8787115418 T DE8787115418 T DE 8787115418T DE 3785133 T DE3785133 T DE 3785133T DE 3785133 T2 DE3785133 T2 DE 3785133T2
- Authority
- DE
- Germany
- Prior art keywords
- arrangement
- bit line
- semiconductor memory
- improved bit
- line arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61251015A JPS63104296A (ja) | 1986-10-21 | 1986-10-21 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3785133D1 DE3785133D1 (de) | 1993-05-06 |
DE3785133T2 true DE3785133T2 (de) | 1993-07-15 |
Family
ID=17216365
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8787115418T Expired - Fee Related DE3785133T2 (de) | 1986-10-21 | 1987-10-21 | Halbleiterspeicheranordnung mit verbesserter bitzeilenordnung. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4872142A (de) |
EP (1) | EP0264929B1 (de) |
JP (1) | JPS63104296A (de) |
DE (1) | DE3785133T2 (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01158694A (ja) * | 1987-12-15 | 1989-06-21 | Mitsubishi Electric Corp | 半導体ダイナミックram |
JP2691280B2 (ja) * | 1988-05-12 | 1997-12-17 | 三菱電機株式会社 | 半導体記憶装置 |
JPH0235765A (ja) * | 1988-07-26 | 1990-02-06 | Nec Corp | 半導体集積回路装置 |
US5062079A (en) * | 1988-09-28 | 1991-10-29 | Kabushiki Kaisha Toshiba | MOS type random access memory with interference noise eliminator |
JP2993671B2 (ja) * | 1989-01-07 | 1999-12-20 | 三菱電機株式会社 | 半導体記憶装置 |
KR920007909B1 (ko) * | 1989-11-18 | 1992-09-19 | 삼성전자 주식회사 | 램 테스트시 고속 기록방법 |
JP2719237B2 (ja) * | 1990-12-20 | 1998-02-25 | シャープ株式会社 | ダイナミック型半導体記憶装置 |
JPH04271086A (ja) * | 1991-02-27 | 1992-09-28 | Nec Corp | 半導体集積回路 |
US5371707A (en) * | 1992-01-30 | 1994-12-06 | Nec Corporation | Dynamic random access memory device equipped with dummy cells implemented by enhancement type transistors |
KR950005095Y1 (ko) * | 1992-03-18 | 1995-06-22 | 문정환 | 양방향성 그로벌 비트 라인을 갖는 dram |
US5475642A (en) * | 1992-06-23 | 1995-12-12 | Taylor; David L. | Dynamic random access memory with bit line preamp/driver |
JP2732762B2 (ja) * | 1992-09-21 | 1998-03-30 | 株式会社東芝 | 半導体記憶装置 |
JP3302796B2 (ja) * | 1992-09-22 | 2002-07-15 | 株式会社東芝 | 半導体記憶装置 |
US5555203A (en) * | 1993-12-28 | 1996-09-10 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device |
US5539695A (en) * | 1995-01-23 | 1996-07-23 | Solidas Corporation | Fast access multi-bit random access memory |
US5708598A (en) * | 1995-04-24 | 1998-01-13 | Saito; Tamio | System and method for reading multiple voltage level memories |
US5958075A (en) * | 1997-09-26 | 1999-09-28 | Advanced Micro Devices, Inc. | Efficient on-pitch scannable sense amplifier |
US6272054B1 (en) | 2000-10-31 | 2001-08-07 | International Business Machines Corporation | Twin-cell memory architecture with shielded bitlines for embedded memory applications |
JP2003056635A (ja) * | 2001-08-17 | 2003-02-26 | Showa Corp | 油圧緩衝器のオイルロック機構 |
US8116157B2 (en) * | 2007-11-20 | 2012-02-14 | Qimonda Ag | Integrated circuit |
US8130556B2 (en) | 2008-10-30 | 2012-03-06 | Sandisk Technologies Inc. | Pair bit line programming to improve boost voltage clamping |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2919166C2 (de) * | 1978-05-12 | 1986-01-02 | Nippon Electric Co., Ltd., Tokio/Tokyo | Speichervorrichtung |
JPS5942399B2 (ja) * | 1979-12-21 | 1984-10-15 | 株式会社日立製作所 | メモリ装置 |
JPS57111061A (en) * | 1980-12-26 | 1982-07-10 | Fujitsu Ltd | Semiconductor memory unit |
JPS5873095A (ja) * | 1981-10-23 | 1983-05-02 | Toshiba Corp | ダイナミツク型メモリ装置 |
JPS5958689A (ja) * | 1982-09-28 | 1984-04-04 | Fujitsu Ltd | 半導体記憶装置 |
EP0139196B1 (de) * | 1983-09-07 | 1989-12-06 | Hitachi, Ltd. | Halbleiterspeicher mit einem Spannungsverstärker des ladungsgekoppelten Typs |
-
1986
- 1986-10-21 JP JP61251015A patent/JPS63104296A/ja active Pending
-
1987
- 1987-10-21 EP EP87115418A patent/EP0264929B1/de not_active Expired - Lifetime
- 1987-10-21 US US07/110,825 patent/US4872142A/en not_active Expired - Lifetime
- 1987-10-21 DE DE8787115418T patent/DE3785133T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPS63104296A (ja) | 1988-05-09 |
US4872142A (en) | 1989-10-03 |
EP0264929A3 (en) | 1990-03-21 |
EP0264929B1 (de) | 1993-03-31 |
DE3785133D1 (de) | 1993-05-06 |
EP0264929A2 (de) | 1988-04-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |