DE3778067D1 - Zweitor-halbleiterspeicheranordnung. - Google Patents

Zweitor-halbleiterspeicheranordnung.

Info

Publication number
DE3778067D1
DE3778067D1 DE8787401282T DE3778067T DE3778067D1 DE 3778067 D1 DE3778067 D1 DE 3778067D1 DE 8787401282 T DE8787401282 T DE 8787401282T DE 3778067 T DE3778067 T DE 3778067T DE 3778067 D1 DE3778067 D1 DE 3778067D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
way semiconductor
way
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787401282T
Other languages
English (en)
Inventor
Hiroshi Nagayama
Fumio Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3778067D1 publication Critical patent/DE3778067D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Multimedia (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE8787401282T 1986-06-06 1987-06-05 Zweitor-halbleiterspeicheranordnung. Expired - Fee Related DE3778067D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61131439A JPS62287497A (ja) 1986-06-06 1986-06-06 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3778067D1 true DE3778067D1 (de) 1992-05-14

Family

ID=15057988

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787401282T Expired - Fee Related DE3778067D1 (de) 1986-06-06 1987-06-05 Zweitor-halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4757477A (de)
EP (1) EP0249548B1 (de)
JP (1) JPS62287497A (de)
KR (1) KR940000148B1 (de)
DE (1) DE3778067D1 (de)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
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US4821226A (en) * 1987-01-30 1989-04-11 Rca Licensing Corporation Dual port video memory system having a bit-serial address input port
US5195056A (en) * 1987-05-21 1993-03-16 Texas Instruments, Incorporated Read/write memory having an on-chip input data register, having pointer circuits between a serial data register and input/output buffer circuits
JPH0748301B2 (ja) * 1987-12-04 1995-05-24 富士通株式会社 半導体記憶装置
JPH01178193A (ja) * 1988-01-07 1989-07-14 Toshiba Corp 半導体記憶装置
JPH07107792B2 (ja) * 1988-01-19 1995-11-15 株式会社東芝 マルチポートメモリ
JP2591010B2 (ja) * 1988-01-29 1997-03-19 日本電気株式会社 シリアルアクセスメモリ装置
US5481496A (en) * 1988-06-27 1996-01-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device and method of data transfer therefor
JP2633645B2 (ja) * 1988-09-13 1997-07-23 株式会社東芝 半導体メモリ装置
JPH07101554B2 (ja) * 1988-11-29 1995-11-01 三菱電機株式会社 半導体記憶装置およびそのデータ転送方法
JP2993671B2 (ja) * 1989-01-07 1999-12-20 三菱電機株式会社 半導体記憶装置
US5442770A (en) * 1989-01-24 1995-08-15 Nec Electronics, Inc. Triple port cache memory
US4984214A (en) * 1989-12-05 1991-01-08 International Business Machines Corporation Multiplexed serial register architecture for VRAM
JP3061824B2 (ja) * 1989-12-18 2000-07-10 松下電子工業株式会社 半導体メモリ
US5341488A (en) * 1990-04-11 1994-08-23 Nec Electronics, Inc. N-word read/write access achieving double bandwidth without increasing the width of external data I/O bus
EP0454162B1 (de) * 1990-04-27 1996-09-25 Nec Corporation Halbleiterspeicheranordnung
GB2246651A (en) * 1990-08-03 1992-02-05 Samsung Electronics Co Ltd Data input circuit for a dual-port memory with block write mode
JP2753129B2 (ja) * 1990-10-02 1998-05-18 株式会社東芝 半導体記憶装置
JPH04315891A (ja) * 1991-04-16 1992-11-06 Nec Corp 画像メモリ
US5291444A (en) * 1991-12-23 1994-03-01 Texas Instruments Incorporated Combination DRAM and SRAM memory array
JPH06349281A (ja) * 1993-06-04 1994-12-22 Fujitsu Ltd 半導体装置
US5442748A (en) * 1993-10-29 1995-08-15 Sun Microsystems, Inc. Architecture of output switching circuitry for frame buffer
KR0141665B1 (ko) * 1994-03-31 1998-07-15 김광호 비디오램 및 시리얼데이타 출력방법
JP2704607B2 (ja) * 1994-08-03 1998-01-26 三菱電機株式会社 半導体記憶装置
US5867721A (en) * 1995-02-07 1999-02-02 Intel Corporation Selecting an integrated circuit from different integrated circuit array configurations
US5671432A (en) * 1995-06-02 1997-09-23 International Business Machines Corporation Programmable array I/O-routing resource
US6097664A (en) * 1999-01-21 2000-08-01 Vantis Corporation Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan
US7170802B2 (en) * 2003-12-31 2007-01-30 Sandisk Corporation Flexible and area efficient column redundancy for non-volatile memories
US6985388B2 (en) 2001-09-17 2006-01-10 Sandisk Corporation Dynamic column block selection
US6560146B2 (en) * 2001-09-17 2003-05-06 Sandisk Corporation Dynamic column block selection
US6848067B2 (en) * 2002-03-27 2005-01-25 Hewlett-Packard Development Company, L.P. Multi-port scan chain register apparatus and method
KR100660871B1 (ko) 2005-07-15 2006-12-26 삼성전자주식회사 연결된 비트라인을 구비하는 반도체 메모리 장치 및 데이터쉬프팅 방법
US7379330B2 (en) * 2005-11-08 2008-05-27 Sandisk Corporation Retargetable memory cell redundancy methods
US8914612B2 (en) 2007-10-29 2014-12-16 Conversant Intellectual Property Management Inc. Data processing with time-based memory access
US8027195B2 (en) * 2009-06-05 2011-09-27 SanDisk Technologies, Inc. Folding data stored in binary format into multi-state format within non-volatile memory devices
US8102705B2 (en) 2009-06-05 2012-01-24 Sandisk Technologies Inc. Structure and method for shuffling data within non-volatile memory devices
US7974124B2 (en) * 2009-06-24 2011-07-05 Sandisk Corporation Pointer based column selection techniques in non-volatile memories
US20110002169A1 (en) 2009-07-06 2011-01-06 Yan Li Bad Column Management with Bit Information in Non-Volatile Memory Systems
US8725935B2 (en) 2009-12-18 2014-05-13 Sandisk Technologies Inc. Balanced performance for on-chip folding of non-volatile memories
US8468294B2 (en) * 2009-12-18 2013-06-18 Sandisk Technologies Inc. Non-volatile memory with multi-gear control using on-chip folding of data
US8144512B2 (en) 2009-12-18 2012-03-27 Sandisk Technologies Inc. Data transfer flows for on-chip folding
US9342446B2 (en) 2011-03-29 2016-05-17 SanDisk Technologies, Inc. Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache
US8842473B2 (en) 2012-03-15 2014-09-23 Sandisk Technologies Inc. Techniques for accessing column selecting shift register with skipped entries in non-volatile memories
US8681548B2 (en) 2012-05-03 2014-03-25 Sandisk Technologies Inc. Column redundancy circuitry for non-volatile memory
US9490035B2 (en) 2012-09-28 2016-11-08 SanDisk Technologies, Inc. Centralized variable rate serializer and deserializer for bad column management
US8897080B2 (en) 2012-09-28 2014-11-25 Sandisk Technologies Inc. Variable rate serial to parallel shift register
US9076506B2 (en) 2012-09-28 2015-07-07 Sandisk Technologies Inc. Variable rate parallel to serial shift register
US9934872B2 (en) 2014-10-30 2018-04-03 Sandisk Technologies Llc Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
US9224502B1 (en) 2015-01-14 2015-12-29 Sandisk Technologies Inc. Techniques for detection and treating memory hole to local interconnect marginality defects
US10032524B2 (en) 2015-02-09 2018-07-24 Sandisk Technologies Llc Techniques for determining local interconnect defects
US9269446B1 (en) 2015-04-08 2016-02-23 Sandisk Technologies Inc. Methods to improve programming of slow cells
US9564219B2 (en) 2015-04-08 2017-02-07 Sandisk Technologies Llc Current based detection and recording of memory hole-interconnect spacing defects

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150190A (en) * 1981-02-27 1982-09-16 Hitachi Ltd Monolithic storage device
US4541076A (en) * 1982-05-13 1985-09-10 Storage Technology Corporation Dual port CMOS random access memory
JPS5975489A (ja) * 1982-10-22 1984-04-28 Hitachi Ltd 半導体記憶装置
JPH0670880B2 (ja) * 1983-01-21 1994-09-07 株式会社日立マイコンシステム 半導体記憶装置
JPS6072020A (ja) * 1983-09-29 1985-04-24 Nec Corp デュアルポ−トメモリ回路
JPS6194290A (ja) * 1984-10-15 1986-05-13 Fujitsu Ltd 半導体メモリ
DE3586523T2 (de) * 1984-10-17 1993-01-07 Fujitsu Ltd Halbleiterspeicheranordnung mit einer seriellen dateneingangs- und ausgangsschaltung.
JPS6196591A (ja) * 1984-10-17 1986-05-15 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
JPS62287497A (ja) 1987-12-14
EP0249548A2 (de) 1987-12-16
KR940000148B1 (ko) 1994-01-07
EP0249548A3 (en) 1989-07-05
US4757477A (en) 1988-07-12
KR880000967A (ko) 1988-03-30
EP0249548B1 (de) 1992-04-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee