DE3772137D1 - Halbleiter-speicheranordnung. - Google Patents

Halbleiter-speicheranordnung.

Info

Publication number
DE3772137D1
DE3772137D1 DE8787112568T DE3772137T DE3772137D1 DE 3772137 D1 DE3772137 D1 DE 3772137D1 DE 8787112568 T DE8787112568 T DE 8787112568T DE 3772137 T DE3772137 T DE 3772137T DE 3772137 D1 DE3772137 D1 DE 3772137D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
arrangement
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787112568T
Other languages
English (en)
Inventor
Yukinori Kodama
Hirohiko Mochizuki
Masao Nakano
Tsuyoshi Ohira
Hidenori Nomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Application granted granted Critical
Publication of DE3772137D1 publication Critical patent/DE3772137D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE8787112568T 1986-09-02 1987-08-28 Halbleiter-speicheranordnung. Expired - Fee Related DE3772137D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61206439A JPS6363196A (ja) 1986-09-02 1986-09-02 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3772137D1 true DE3772137D1 (de) 1991-09-19

Family

ID=16523394

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787112568T Expired - Fee Related DE3772137D1 (de) 1986-09-02 1987-08-28 Halbleiter-speicheranordnung.

Country Status (5)

Country Link
US (1) US4799197A (de)
EP (1) EP0260503B1 (de)
JP (1) JPS6363196A (de)
KR (1) KR910009442B1 (de)
DE (1) DE3772137D1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5189639A (en) * 1987-11-26 1993-02-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having bit lines capable of partial operation
US5148399A (en) * 1988-06-28 1992-09-15 Oki Electric Industry Co., Ltd. Sense amplifier circuitry selectively separable from bit lines for dynamic random access memory
JPH07109702B2 (ja) * 1988-09-12 1995-11-22 株式会社東芝 ダイナミック型メモリ
KR910009444B1 (ko) * 1988-12-20 1991-11-16 삼성전자 주식회사 반도체 메모리 장치
KR920005150A (ko) * 1990-08-31 1992-03-28 김광호 씨모오스디램의 센스 앰프 구성방법
JPH04125891A (ja) * 1990-09-17 1992-04-27 Oki Electric Ind Co Ltd 半導体記憶装置
DE69121503T2 (de) * 1990-09-29 1997-02-13 Nippon Electric Co Halbleiterspeicheranordnung mit einer rauscharmen Abfühlstruktur
JP2704041B2 (ja) * 1990-11-09 1998-01-26 日本電気アイシーマイコンシステム株式会社 半導体メモリ装置
JP3076606B2 (ja) * 1990-12-14 2000-08-14 富士通株式会社 半導体記憶装置およびその検査方法
US5226014A (en) * 1990-12-24 1993-07-06 Ncr Corporation Low power pseudo-static ROM
JPH04258875A (ja) * 1991-02-14 1992-09-14 Sharp Corp 半導体メモリ装置
US5384726A (en) * 1993-03-18 1995-01-24 Fujitsu Limited Semiconductor memory device having a capability for controlled activation of sense amplifiers
JP3178946B2 (ja) * 1993-08-31 2001-06-25 沖電気工業株式会社 半導体記憶装置及びその駆動方法
US5721875A (en) * 1993-11-12 1998-02-24 Intel Corporation I/O transceiver having a pulsed latch receiver circuit
US5907516A (en) * 1994-07-07 1999-05-25 Hyundai Electronics Industries Co., Ltd. Semiconductor memory device with reduced data bus line load
US6504745B2 (en) * 1996-05-24 2003-01-07 Uniram Technology, Inc. High performance erasable programmable read-only memory (EPROM) devices with multiple dimension first-level bit lines
JPH10334662A (ja) * 1997-05-29 1998-12-18 Nec Corp 半導体記憶装置
JP2001118999A (ja) * 1999-10-15 2001-04-27 Hitachi Ltd ダイナミック型ｒａｍと半導体装置
EP1310963B1 (de) * 2000-06-29 2006-12-27 Fujitsu Limited Halbleiter-speicherbaustein
US6667922B1 (en) * 2002-08-21 2003-12-23 Infineon Technologies Ag Sensing amplifier with single sided writeback
JP2005322380A (ja) * 2004-04-09 2005-11-17 Toshiba Corp 半導体記憶装置
JP2008077805A (ja) 2006-09-25 2008-04-03 Fujitsu Ltd 半導体記憶装置及びタイミング制御方法
JP6106043B2 (ja) * 2013-07-25 2017-03-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2919166C2 (de) * 1978-05-12 1986-01-02 Nippon Electric Co., Ltd., Tokio/Tokyo Speichervorrichtung
US4274013A (en) * 1979-02-09 1981-06-16 Bell Telephone Laboratories, Incorporated Sense amplifier
JPS5931155B2 (ja) * 1979-10-11 1984-07-31 インターナシヨナルビジネス マシーンズ コーポレーシヨン 感知増幅回路
WO1981003572A1 (en) * 1980-06-02 1981-12-10 Mostek Corp Semiconductor memory precharge circuit
US4363111A (en) * 1980-10-06 1982-12-07 Heightley John D Dummy cell arrangement for an MOS memory
JPS5782286A (en) * 1980-11-06 1982-05-22 Mitsubishi Electric Corp Semiconductor storage device
JPS5873095A (ja) * 1981-10-23 1983-05-02 Toshiba Corp ダイナミツク型メモリ装置
JPH069114B2 (ja) * 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
US4584672A (en) * 1984-02-22 1986-04-22 Intel Corporation CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge
JPS6194296A (ja) * 1984-10-16 1986-05-13 Fujitsu Ltd 半導体記憶装置
US4745577A (en) * 1984-11-20 1988-05-17 Fujitsu Limited Semiconductor memory device with shift registers for high speed reading and writing

Also Published As

Publication number Publication date
EP0260503B1 (de) 1991-08-14
JPS6363196A (ja) 1988-03-19
KR880004478A (ko) 1988-06-04
US4799197A (en) 1989-01-17
KR910009442B1 (ko) 1991-11-16
EP0260503A1 (de) 1988-03-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee