DE3777927D1 - Halbleiterspeicheranordnung mit geteilten bitleitungen. - Google Patents

Halbleiterspeicheranordnung mit geteilten bitleitungen.

Info

Publication number
DE3777927D1
DE3777927D1 DE8787308270T DE3777927T DE3777927D1 DE 3777927 D1 DE3777927 D1 DE 3777927D1 DE 8787308270 T DE8787308270 T DE 8787308270T DE 3777927 T DE3777927 T DE 3777927T DE 3777927 D1 DE3777927 D1 DE 3777927D1
Authority
DE
Germany
Prior art keywords
bit lines
semiconductor storage
storage arrangement
divided bit
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787308270T
Other languages
English (en)
Inventor
Kimiaki Sato
Tool Khono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3777927D1 publication Critical patent/DE3777927D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE8787308270T 1986-09-18 1987-09-18 Halbleiterspeicheranordnung mit geteilten bitleitungen. Expired - Fee Related DE3777927D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61218170A JPH07118193B2 (ja) 1986-09-18 1986-09-18 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3777927D1 true DE3777927D1 (de) 1992-05-07

Family

ID=16715721

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787308270T Expired - Fee Related DE3777927D1 (de) 1986-09-18 1987-09-18 Halbleiterspeicheranordnung mit geteilten bitleitungen.

Country Status (5)

Country Link
US (1) US4839868A (de)
EP (1) EP0260983B1 (de)
JP (1) JPH07118193B2 (de)
KR (1) KR910004734B1 (de)
DE (1) DE3777927D1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5249159A (en) * 1987-05-27 1993-09-28 Hitachi, Ltd. Semiconductor memory
US5274596A (en) * 1987-09-16 1993-12-28 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device having simultaneous operation of adjacent blocks
US5481496A (en) * 1988-06-27 1996-01-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device and method of data transfer therefor
JP2729302B2 (ja) * 1988-06-27 1998-03-18 三菱電機株式会社 半導体記憶装置におけるデータ転送方法
NL8802125A (nl) * 1988-08-29 1990-03-16 Philips Nv Geintegreerde geheugenschakeling met parallelle en seriele in- en uitgang.
JPH0283892A (ja) * 1988-09-20 1990-03-23 Fujitsu Ltd 半導体記憶装置
JPH07101554B2 (ja) * 1988-11-29 1995-11-01 三菱電機株式会社 半導体記憶装置およびそのデータ転送方法
JP2761515B2 (ja) * 1989-03-08 1998-06-04 株式会社日立製作所 半導体記憶装置
US5276649A (en) * 1989-03-16 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Dynamic-type semiconductor memory device having staggered activation of column groups
JPH0341697A (ja) * 1989-07-10 1991-02-22 Nec Ic Microcomput Syst Ltd 半導体メモリ
JP2759689B2 (ja) * 1989-11-24 1998-05-28 松下電器産業株式会社 Ｒａｍの読み出し回路
JPH03245396A (ja) * 1990-02-22 1991-10-31 Sharp Corp ダイナミック型半導体記憶装置
JPH0447587A (ja) * 1990-06-15 1992-02-17 Oki Electric Ind Co Ltd 半導体記憶装置
JP3039793B2 (ja) * 1990-07-05 2000-05-08 株式会社東芝 半導体メモリ装置
EP0488265B1 (de) * 1990-11-30 1996-08-14 Kabushiki Kaisha Toshiba Halbleiterspeicheranordnung
US5245584A (en) * 1990-12-20 1993-09-14 Vlsi Technology, Inc. Method and apparatus for compensating for bit line delays in semiconductor memories
JP3048668B2 (ja) * 1991-03-28 2000-06-05 日本電気株式会社 半導体メモリ装置
US5561630A (en) * 1995-09-28 1996-10-01 International Business Machines Coporation Data sense circuit for dynamic random access memories
US5671188A (en) * 1996-06-26 1997-09-23 Alliance Semiconductor Corporation Random access memory having selective intra-bank fast activation of sense amplifiers
US7051264B2 (en) * 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
US7392456B2 (en) * 2004-11-23 2008-06-24 Mosys, Inc. Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4162540A (en) * 1978-03-20 1979-07-24 Fujitsu Limited Clocked memory with delay establisher by drive transistor design
US4281401A (en) * 1979-11-23 1981-07-28 Texas Instruments Incorporated Semiconductor read/write memory array having high speed serial shift register access
JPS57150197A (en) * 1981-03-11 1982-09-16 Nippon Telegr & Teleph Corp <Ntt> Storage circuit
JPS5880189A (ja) * 1981-11-05 1983-05-14 Fujitsu Ltd 半導体記憶装置
JPS5880188A (ja) * 1981-11-05 1983-05-14 Fujitsu Ltd 半導体記憶装置
JPS5948889A (ja) * 1982-09-10 1984-03-21 Hitachi Ltd Ｍｏｓ記憶装置
JPS59101095A (ja) * 1982-11-29 1984-06-11 Toshiba Corp 不揮発性半導体メモリ
JPS59104791A (ja) * 1982-12-04 1984-06-16 Fujitsu Ltd 半導体記憶装置
EP0166642A3 (de) * 1984-05-30 1989-02-22 Fujitsu Limited Blockunterteiltes Halbleiterspeichergerät mit unterteilten Bitzeilen
JPS61110394A (ja) * 1984-10-31 1986-05-28 Mitsubishi Electric Corp 半導体記憶装置
KR900005667B1 (ko) * 1984-11-20 1990-08-03 후지쓰 가부시끼가이샤 반도체 기억장치

Also Published As

Publication number Publication date
EP0260983B1 (de) 1992-04-01
US4839868A (en) 1989-06-13
EP0260983A3 (en) 1990-08-29
KR880004482A (ko) 1988-06-04
EP0260983A2 (de) 1988-03-23
KR910004734B1 (ko) 1991-07-10
JPH07118193B2 (ja) 1995-12-18
JPS6374199A (ja) 1988-04-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee