DE69111731T2 - Verfahren zur Herstellung von Markierungen zum Alignieren von Marken. - Google Patents

Verfahren zur Herstellung von Markierungen zum Alignieren von Marken.

Info

Publication number
DE69111731T2
DE69111731T2 DE69111731T DE69111731T DE69111731T2 DE 69111731 T2 DE69111731 T2 DE 69111731T2 DE 69111731 T DE69111731 T DE 69111731T DE 69111731 T DE69111731 T DE 69111731T DE 69111731 T2 DE69111731 T2 DE 69111731T2
Authority
DE
Germany
Prior art keywords
marks
producing
aligning
aligning marks
producing marks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69111731T
Other languages
English (en)
Other versions
DE69111731D1 (de
Inventor
Der Plas Paulus Van
Herbert Lifka
Robertus Verhaar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Application granted granted Critical
Publication of DE69111731D1 publication Critical patent/DE69111731D1/de
Publication of DE69111731T2 publication Critical patent/DE69111731T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment
DE69111731T 1990-09-28 1991-09-19 Verfahren zur Herstellung von Markierungen zum Alignieren von Marken. Expired - Fee Related DE69111731T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9011979A FR2667440A1 (fr) 1990-09-28 1990-09-28 Procede pour realiser des motifs d'alignement de masques.

Publications (2)

Publication Number Publication Date
DE69111731D1 DE69111731D1 (de) 1995-09-07
DE69111731T2 true DE69111731T2 (de) 1996-03-21

Family

ID=9400745

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69111731T Expired - Fee Related DE69111731T2 (de) 1990-09-28 1991-09-19 Verfahren zur Herstellung von Markierungen zum Alignieren von Marken.

Country Status (6)

Country Link
US (1) US5316966A (de)
EP (1) EP0478072B1 (de)
JP (1) JPH0744146B2 (de)
KR (1) KR100229560B1 (de)
DE (1) DE69111731T2 (de)
FR (1) FR2667440A1 (de)

Families Citing this family (46)

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US5503962A (en) * 1994-07-15 1996-04-02 Cypress Semiconductor Corporation Chemical-mechanical alignment mark and method of fabrication
US5795809A (en) * 1995-05-25 1998-08-18 Advanced Micro Devices, Inc. Semiconductor wafer fabrication process including gettering utilizing a combined oxidation technique
KR0155835B1 (ko) * 1995-06-23 1998-12-01 김광호 반도체 장치의 얼라인 키 패턴 형성방법
JP3528350B2 (ja) * 1995-08-25 2004-05-17 ソニー株式会社 半導体装置の製造方法
KR100257167B1 (ko) * 1995-09-29 2000-05-15 김영환 반도체 소자의 제조방법
JP3634505B2 (ja) * 1996-05-29 2005-03-30 株式会社ルネサステクノロジ アライメントマーク配置方法
US5700732A (en) * 1996-08-02 1997-12-23 Micron Technology, Inc. Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns
US5858854A (en) * 1996-10-16 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high contrast alignment marks
KR100236097B1 (ko) * 1996-10-30 1999-12-15 김영환 반도체 장치의 격리막 형성방법
US5936311A (en) * 1996-12-31 1999-08-10 Intel Corporation Integrated circuit alignment marks distributed throughout a surface metal line
US5956564A (en) * 1997-06-03 1999-09-21 Ultratech Stepper, Inc. Method of making a side alignment mark
US6306727B1 (en) * 1997-08-18 2001-10-23 Micron Technology, Inc. Advanced isolation process for large memory arrays
JP4187808B2 (ja) 1997-08-25 2008-11-26 株式会社ルネサステクノロジ 半導体装置の製造方法
US6303460B1 (en) * 2000-02-07 2001-10-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US6440819B1 (en) * 1998-03-03 2002-08-27 Advanced Micro Devices, Inc. Method for differential trenching in conjunction with differential fieldox growth
US5966618A (en) * 1998-03-06 1999-10-12 Advanced Micro Devices, Inc. Method of forming dual field isolation structures
US6249036B1 (en) 1998-03-18 2001-06-19 Advanced Micro Devices, Inc. Stepper alignment mark formation with dual field oxide process
US6327513B1 (en) * 1998-04-16 2001-12-04 Vlsi Technology, Inc. Methods and apparatus for calculating alignment of layers during semiconductor processing
US6043133A (en) * 1998-07-24 2000-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of photo alignment for shallow trench isolation chemical-mechanical polishing
US6303458B1 (en) 1998-10-05 2001-10-16 Chartered Semiconductor Manufacturing Ltd. Alignment mark scheme for Sti process to save one mask step
FR2784797B1 (fr) * 1998-10-14 2002-08-23 St Microelectronics Sa Procede de fabrication d'un circuit integre
WO2000024057A1 (en) * 1998-10-20 2000-04-27 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device in a silicon body, a surface of said silicon body being provided with a grating and an at least partially recessed oxide pattern
US6054361A (en) * 1999-02-11 2000-04-25 Chartered Semiconductor Manufacturing, Ltd. Preserving the zero mark for wafer alignment
US6221737B1 (en) * 1999-09-30 2001-04-24 Philips Electronics North America Corporation Method of making semiconductor devices with graded top oxide and graded drift region
US7057299B2 (en) * 2000-02-03 2006-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Alignment mark configuration
JP3970546B2 (ja) * 2001-04-13 2007-09-05 沖電気工業株式会社 半導体装置及び半導体装置の製造方法
US6500725B1 (en) * 2001-09-06 2002-12-31 Taiwan Semiconductor Manufacturing Company, Ltd Microelectronic fabrication method providing alignment mark and isolation trench of identical depth
US6623911B1 (en) 2001-09-17 2003-09-23 Taiwan Semiconductor Manufacturing Company Method to form code marks on mask ROM products
US20030109113A1 (en) * 2001-12-07 2003-06-12 Wen-Ying Wen Method of making identification code of ROM and structure thereof
US7518182B2 (en) 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US7247570B2 (en) * 2004-08-19 2007-07-24 Micron Technology, Inc. Silicon pillars for vertical transistors
US7285812B2 (en) 2004-09-02 2007-10-23 Micron Technology, Inc. Vertical transistors
US7199419B2 (en) * 2004-12-13 2007-04-03 Micron Technology, Inc. Memory structure for reduced floating body effect
US7229895B2 (en) * 2005-01-14 2007-06-12 Micron Technology, Inc Memory array buried digit line
US7120046B1 (en) 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7371627B1 (en) 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
CN101207064B (zh) * 2006-12-22 2010-08-11 中芯国际集成电路制造(上海)有限公司 器件隔离区的形成方法
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
JP5571283B2 (ja) * 2007-12-25 2014-08-13 ローム株式会社 半導体装置
KR101031288B1 (ko) 2009-09-25 2011-04-29 전자부품연구원 질화물 금속 구조 및 이의 제조 방법
US9401363B2 (en) 2011-08-23 2016-07-26 Micron Technology, Inc. Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
US9230917B2 (en) * 2013-05-29 2016-01-05 Infineon Technologies Dresden Gmbh Method of processing a carrier with alignment marks
JP6198337B2 (ja) * 2014-06-25 2017-09-20 ローム株式会社 半導体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4338620A (en) * 1978-08-31 1982-07-06 Fujitsu Limited Semiconductor devices having improved alignment marks
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
JPS5972724A (ja) * 1982-10-20 1984-04-24 Hitachi Ltd 位置合せ方法
JPS59158519A (ja) * 1983-02-28 1984-09-08 Toshiba Corp 半導体装置の製造方法
JPS6097639A (ja) * 1983-11-01 1985-05-31 Toshiba Corp 半導体装置の製造方法
JPS61100928A (ja) * 1984-10-22 1986-05-19 Mitsubishi Electric Corp 半導体基板の位置合せマ−ク形成方法
JPS61222137A (ja) * 1985-03-06 1986-10-02 Sharp Corp チップ識別用凹凸パターン形成方法
JP2710935B2 (ja) * 1987-08-08 1998-02-10 三菱電機株式会社 半導体装置
US4893163A (en) * 1988-03-28 1990-01-09 International Business Machines Corporation Alignment mark system for electron beam/optical mixed lithography
KR0177148B1 (ko) * 1989-05-16 1999-04-15 고스기 노부미쓰 웨이퍼 얼라인먼트 마크 및 그 제조방법

Also Published As

Publication number Publication date
KR920007141A (ko) 1992-04-28
JPH0744146B2 (ja) 1995-05-15
JPH04234108A (ja) 1992-08-21
FR2667440A1 (fr) 1992-04-03
EP0478072A1 (de) 1992-04-01
EP0478072B1 (de) 1995-08-02
US5316966A (en) 1994-05-31
DE69111731D1 (de) 1995-09-07
KR100229560B1 (ko) 1999-11-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee