DE68917504T2 - Verfahren zur Herstellung von abwechselnden Schichten aus monokristallinen Halbleitermaterial und Schichten aus isolierendem Material. - Google Patents

Verfahren zur Herstellung von abwechselnden Schichten aus monokristallinen Halbleitermaterial und Schichten aus isolierendem Material.

Info

Publication number
DE68917504T2
DE68917504T2 DE68917504T DE68917504T DE68917504T2 DE 68917504 T2 DE68917504 T2 DE 68917504T2 DE 68917504 T DE68917504 T DE 68917504T DE 68917504 T DE68917504 T DE 68917504T DE 68917504 T2 DE68917504 T2 DE 68917504T2
Authority
DE
Germany
Prior art keywords
layers
production
monocrystalline semiconductor
insulating material
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68917504T
Other languages
English (en)
Other versions
DE68917504D1 (de
Inventor
Didier Pribat
Leonidas Karapiperis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
REMOTE ACCESS,LLC, LOS ALTOS, CALIF., US
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Application granted granted Critical
Publication of DE68917504D1 publication Critical patent/DE68917504D1/de
Publication of DE68917504T2 publication Critical patent/DE68917504T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76248—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using lateral overgrowth techniques, i.e. ELO techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02549—Antimonides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V
DE68917504T 1988-04-05 1989-04-04 Verfahren zur Herstellung von abwechselnden Schichten aus monokristallinen Halbleitermaterial und Schichten aus isolierendem Material. Expired - Lifetime DE68917504T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8804438A FR2629637B1 (fr) 1988-04-05 1988-04-05 Procede de realisation d'une alternance de couches de materiau semiconducteur monocristallin et de couches de materiau isolant

Publications (2)

Publication Number Publication Date
DE68917504D1 DE68917504D1 (de) 1994-09-22
DE68917504T2 true DE68917504T2 (de) 1994-12-15

Family

ID=9364939

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68917504T Expired - Lifetime DE68917504T2 (de) 1988-04-05 1989-04-04 Verfahren zur Herstellung von abwechselnden Schichten aus monokristallinen Halbleitermaterial und Schichten aus isolierendem Material.

Country Status (5)

Country Link
US (1) US4999314A (de)
EP (1) EP0336831B1 (de)
JP (1) JP2889589B2 (de)
DE (1) DE68917504T2 (de)
FR (1) FR2629637B1 (de)

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JP2527016B2 (ja) * 1988-11-11 1996-08-21 日本電気株式会社 半導体膜の製造方法
US4975385A (en) * 1990-04-06 1990-12-04 Applied Materials, Inc. Method of constructing lightly doped drain (LDD) integrated circuit structure
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FR2667617B1 (fr) * 1990-10-09 1992-11-27 Thomson Csf Procede de croissance de couches heteroepitaxiales.
JPH04299569A (ja) * 1991-03-27 1992-10-22 Nec Corp Ｓｏｉｓの製造方法及びトランジスタとその製造方法
US5525550A (en) * 1991-05-21 1996-06-11 Fujitsu Limited Process for forming thin films by plasma CVD for use in the production of semiconductor devices
EP0809279B1 (de) * 1991-09-23 2003-02-19 Infineon Technologies AG Verfahren zur Herstellung eines MOS-Transistors
FR2682128B1 (fr) * 1991-10-08 1993-12-03 Thomson Csf Procede de croissance de couches heteroepitaxiales.
US5273921A (en) * 1991-12-27 1993-12-28 Purdue Research Foundation Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
US5328868A (en) * 1992-01-14 1994-07-12 International Business Machines Corporation Method of forming metal connections
FR2689680B1 (fr) * 1992-04-02 2001-08-10 Thomson Csf Procédé de réalisation de couches minces hétéroépitaxiales et de dispositifs électroniques.
US5302544A (en) * 1992-12-17 1994-04-12 Eastman Kodak Company Method of making CCD having a single level electrode of single crystalline silicon
US5610441A (en) * 1995-05-19 1997-03-11 International Business Machines Corporation Angle defined trench conductor for a semiconductor device
US6294440B1 (en) * 1998-04-10 2001-09-25 Sharp Kabushiki Kaisha Semiconductor substrate, light-emitting device, and method for producing the same
FR2780808B1 (fr) 1998-07-03 2001-08-10 Thomson Csf Dispositif a emission de champ et procedes de fabrication
US5981363A (en) * 1998-11-17 1999-11-09 Gardner; Mark I. Method and apparatus for high performance transistor devices
JP3470623B2 (ja) * 1998-11-26 2003-11-25 ソニー株式会社 窒化物系ｉｉｉ−ｖ族化合物半導体の成長方法、半導体装置の製造方法および半導体装置
JP2002110662A (ja) * 2000-09-29 2002-04-12 Toshiba Corp 半導体装置の製造方法および半導体装置
JP2002270516A (ja) * 2001-03-07 2002-09-20 Nec Corp Ｉｉｉ族窒化物半導体の成長方法、ｉｉｉ族窒化物半導体膜およびそれを用いた半導体素子
FR2832995B1 (fr) * 2001-12-04 2004-02-27 Thales Sa Procede de croissance catalytique de nanotubes ou nanofibres comprenant une barriere de diffusion de type alliage nisi
US6972228B2 (en) * 2003-03-12 2005-12-06 Intel Corporation Method of forming an element of a microelectronic circuit
US7514285B2 (en) * 2006-01-17 2009-04-07 Honeywell International Inc. Isolation scheme for reducing film stress in a MEMS device
TWI309439B (en) * 2006-09-05 2009-05-01 Ind Tech Res Inst Nitride semiconductor and method for forming the same
US20110233689A1 (en) * 2008-12-08 2011-09-29 Sumitomo Chemical Company, Limited Semiconductor device, process for producing semiconductor device, semiconductor substrate, and process for producing semiconductor substrate
US8313967B1 (en) 2009-01-21 2012-11-20 Stc.Unm Cubic phase, nitrogen-based compound semiconductor films epitaxially grown on a grooved Si <001> substrate
US20120025195A1 (en) * 2010-07-28 2012-02-02 Massachusetts Institute Of Technology Confined Lateral Growth of Crystalline Material
CN103764881A (zh) * 2011-05-17 2014-04-30 麦克马斯特大学 通过横向扩散液相外延的半导体形成
US20150001588A1 (en) * 2012-02-13 2015-01-01 Tokyo Electron Limited Semiconductor device and method for manufacturing same
WO2013165620A1 (en) 2012-05-04 2013-11-07 Stc.Unm Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure
US10164082B2 (en) 2012-05-04 2018-12-25 Stc.Unm Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure
US10453996B2 (en) 2012-05-04 2019-10-22 Stc.Unm Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure
US9879357B2 (en) 2013-03-11 2018-01-30 Tivra Corporation Methods and systems for thin film deposition processes
US9487885B2 (en) 2012-06-14 2016-11-08 Tivra Corporation Substrate structures and methods
WO2013188574A2 (en) * 2012-06-14 2013-12-19 Tivra Corporation Multilayer substrate structure and method and system of manufacturing the same
US20150059640A1 (en) * 2013-08-27 2015-03-05 Raytheon Company Method for reducing growth of non-uniformities and autodoping during column iii-v growth into dielectric windows
GB201321949D0 (en) 2013-12-12 2014-01-29 Ibm Semiconductor nanowire fabrication
DE102014205364A1 (de) * 2014-03-21 2015-09-24 Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik Herstellung von Halbleiter-auf-Isolator-Schichtstrukturen
KR102430501B1 (ko) * 2015-12-29 2022-08-09 삼성전자주식회사 반도체 단결정구조, 반도체 디바이스 및 그 제조방법
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US9735010B1 (en) 2016-05-27 2017-08-15 International Business Machines Corporation Fabrication of semiconductor fin structures
WO2021192075A1 (ja) * 2020-03-25 2021-09-30 日本電信電話株式会社 半導体層の形成方法
JPWO2023276107A1 (de) * 2021-07-01 2023-01-05

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Also Published As

Publication number Publication date
EP0336831A1 (de) 1989-10-11
DE68917504D1 (de) 1994-09-22
US4999314A (en) 1991-03-12
JP2889589B2 (ja) 1999-05-10
FR2629637A1 (fr) 1989-10-06
JPH0210825A (ja) 1990-01-16
FR2629637B1 (fr) 1990-11-16
EP0336831B1 (de) 1994-08-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: THALES, PARIS, FR

8328 Change in the person/name/address of the agent

Representative=s name: BOEHMERT & BOEHMERT, 28209 BREMEN

8327 Change in the person/name/address of the patent owner

Owner name: REMOTE ACCESS,LLC, LOS ALTOS, CALIF., US