DE68915619D1 - Herstellungsverfahren von Halbleiteranordnungen, die mindestens eine reaktive ionische Ätzstufe enthalten. - Google Patents

Herstellungsverfahren von Halbleiteranordnungen, die mindestens eine reaktive ionische Ätzstufe enthalten.

Info

Publication number
DE68915619D1
DE68915619D1 DE68915619T DE68915619T DE68915619D1 DE 68915619 D1 DE68915619 D1 DE 68915619D1 DE 68915619 T DE68915619 T DE 68915619T DE 68915619 T DE68915619 T DE 68915619T DE 68915619 D1 DE68915619 D1 DE 68915619D1
Authority
DE
Germany
Prior art keywords
contain
manufacturing
semiconductor devices
etching stage
reactive ionic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68915619T
Other languages
English (en)
Other versions
DE68915619T2 (de
Inventor
Philippe Autier
Jean-Marc Auger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE68915619D1 publication Critical patent/DE68915619D1/de
Application granted granted Critical
Publication of DE68915619T2 publication Critical patent/DE68915619T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
DE68915619T 1988-06-24 1989-06-19 Herstellungsverfahren von Halbleiteranordnungen, die mindestens eine reaktive ionische Ätzstufe enthalten. Expired - Fee Related DE68915619T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8808504A FR2633451B1 (fr) 1988-06-24 1988-06-24 Procede de realisation de dispositifs semiconducteurs incluant au moins une etape de gravure ionique reactive

Publications (2)

Publication Number Publication Date
DE68915619D1 true DE68915619D1 (de) 1994-07-07
DE68915619T2 DE68915619T2 (de) 1994-12-22

Family

ID=9367677

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68915619T Expired - Fee Related DE68915619T2 (de) 1988-06-24 1989-06-19 Herstellungsverfahren von Halbleiteranordnungen, die mindestens eine reaktive ionische Ätzstufe enthalten.

Country Status (6)

Country Link
US (1) US4925813A (de)
EP (1) EP0347992B1 (de)
JP (1) JPH0680645B2 (de)
KR (1) KR0139541B1 (de)
DE (1) DE68915619T2 (de)
FR (1) FR2633451B1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053105A (en) * 1990-07-19 1991-10-01 Micron Technology, Inc. Process for creating an etch mask suitable for deep plasma etches employing self-aligned silicidation of a metal layer masked with a silicon dioxide template
US5068007A (en) * 1990-09-24 1991-11-26 Motorola, Inc. Etching of materials in a noncorrosive environment
EP0503473A3 (en) * 1991-03-12 1992-10-28 Texas Instruments Incorporated Method of dry etching ina1as and ingaas lattice matched to inp
DE4317722C2 (de) * 1993-05-27 1996-12-05 Siemens Ag Verfahren zum anisotropen Ätzen einer aluminiumhaltigen Schicht und Verwendung einer hierzu geeigneten Ätzgasmischung
US5946594A (en) * 1996-01-02 1999-08-31 Micron Technology, Inc. Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants
JPH09326298A (ja) * 1996-04-01 1997-12-16 Denso Corp ドライエッチング方法及びｅｌ素子の製造方法
KR100374228B1 (ko) * 2001-03-28 2003-03-03 주식회사 하이닉스반도체 금속배선 형성 방법
JP4030982B2 (ja) * 2004-05-10 2008-01-09 ユーディナデバイス株式会社 半導体装置および半導体装置の製造方法
KR100759808B1 (ko) * 2005-12-08 2007-09-20 한국전자통신연구원 Ｉｉｉ－ｖ 족 반도체 다층구조의 식각 방법 및 이를이용한 수직공진형 표면방출 레이저 제조 방법
US20070161529A1 (en) * 2005-12-22 2007-07-12 Tosoh Corporation Cleaning composition for semiconductor device-manufacturing apparatus and cleaning method
JP2008098456A (ja) * 2006-10-13 2008-04-24 Eudyna Devices Inc 半導体装置の製造方法
CN102110592A (zh) * 2010-12-02 2011-06-29 南京大学扬州光电研究院 用于干法刻蚀的蓝宝石衬底表面加工前期生产方法
DE102013100035B4 (de) 2012-05-24 2019-10-24 Universität Kassel Ätzverfahren für III-V Halbleitermaterialien
US11756793B2 (en) * 2019-12-27 2023-09-12 Hitachi High-Tech Corporation Semiconductor device manufacturing method
CN113053744B (zh) * 2019-12-27 2024-03-22 株式会社日立高新技术 半导体装置的制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5914893B2 (ja) * 1975-09-08 1984-04-06 ソニー株式会社 ガリウム砒素系化合物半導体用エツチング液
US4467521A (en) * 1983-08-15 1984-08-28 Sperry Corporation Selective epitaxial growth of gallium arsenide with selective orientation
US4840922A (en) * 1986-07-29 1989-06-20 Ricoh Company, Ltd. Method of manufacturing masked semiconductor laser
FR2613381B1 (fr) * 1987-04-01 1989-06-23 Cit Alcatel Procede d'attaque d'une surface d'une piece en phosphure d'indium
US4771017A (en) * 1987-06-23 1988-09-13 Spire Corporation Patterning process

Also Published As

Publication number Publication date
US4925813A (en) 1990-05-15
FR2633451A1 (fr) 1989-12-29
DE68915619T2 (de) 1994-12-22
KR910001871A (ko) 1991-01-31
EP0347992A1 (de) 1989-12-27
EP0347992B1 (de) 1994-06-01
JPH0244721A (ja) 1990-02-14
JPH0680645B2 (ja) 1994-10-12
KR0139541B1 (ko) 1998-07-15
FR2633451B1 (fr) 1990-10-05

Similar Documents

Publication Publication Date Title
DE68915619D1 (de) Herstellungsverfahren von Halbleiteranordnungen, die mindestens eine reaktive ionische Ätzstufe enthalten.
DE68919408D1 (de) Verbindungshalbleiter, denselben anwendendes Halbleiter-Bauelement und Herstellungsverfahren des Halbleiter-Bauelementes.
IT7926806A0 (it) Processo perfezionato per la fabbricazione di dispositivi semiconduttori.
DE3577912D1 (de) Interferometrische methoden fuer die fabrikation von halbleitervorrichtungen.
IT7922195A0 (it) Processo perfezionato per la fabbricazione di dispositivi semiconduttori.
DE3789069T2 (de) Verarbeitung einer Halbleiterscheibe.
DE3775430D1 (de) Mehrfachverglasung, sowie herstellungsverfahren und vorrichtung hierfuer.
DE3784130D1 (de) Kuehlung von objekten, zum beispiel halbleiteranordnungen.
IT8422056A0 (it) Substrato semiconduttore e processo di realizzazione dello stesso.
IT7823833A0 (it) Processo di fabbricazione di dispositivi semiconduttori.
DE3789826T2 (de) MOS-Halbleiteranordnung und Herstellungsverfahren.
DE69006434T2 (de) Herstellungsverfahren einer Halbleiteranordnung.
DE3789393D1 (de) Herstellungsverfahren von Halbleiter-Scheiben.
IT8523417A0 (it) Procedimento per la valutazione dei parametri di processo nella fabbricazione di dispositivi a semiconduttore.
IT7927119A0 (it) Processo e relativo apparato per la metallizzazione di dispositivi semiconduttori.
KR900008697A (ko) 반도체 웨이퍼 제조방법
BR8707876A (pt) Processo de fabricacao de dispositivos semicondutores
EP0148448A3 (de) Ätzverfahren
IT7826098A0 (it) Processo per la fabbricazione di dispositivi semiconduttori.
DE68914572T2 (de) Verfahren zum Herstellen von Halbleitervorrichtungen.
IT8224680A0 (it) Procedimento di fabbricazione di dispositivi semiconduttori e dispositivi semi-conduttori cosi'ottenuti.
DE3785292D1 (de) Hochleistungslasermaske und herstellungsverfahren.
DE3888294D1 (de) Eingangsschaltung, die in eine Halbleiteranlage eingegliedert ist.
DE69017949D1 (de) Verfahren zum Herstellen von Halbleiteranordnungen.
DE68910873T2 (de) Herstellungsverfahren von Halbleitervorrichtungen.

Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee