KR900008697A - 반도체 웨이퍼 제조방법 - Google Patents
반도체 웨이퍼 제조방법Info
- Publication number
- KR900008697A KR900008697A KR1019890016068A KR890016068A KR900008697A KR 900008697 A KR900008697 A KR 900008697A KR 1019890016068 A KR1019890016068 A KR 1019890016068A KR 890016068 A KR890016068 A KR 890016068A KR 900008697 A KR900008697 A KR 900008697A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor wafer
- wafer manufacturing
- manufacturing
- semiconductor
- wafer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/012—Bonding, e.g. electrostatic for strain gauges
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/135—Removal of substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28459088A JP2689536B2 (ja) | 1988-11-09 | 1988-11-09 | 半導体ウエハの製造方法 |
JP284590 | 1988-11-09 | ||
JP8300 | 1989-01-17 | ||
JP830089A JPH02188968A (ja) | 1989-01-17 | 1989-01-17 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900008697A true KR900008697A (ko) | 1990-06-03 |
KR0144461B1 KR0144461B1 (ko) | 1998-08-17 |
Family
ID=26342793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890016068A KR0144461B1 (ko) | 1988-11-09 | 1989-11-07 | 반도체 웨이퍼 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5051378A (ko) |
EP (1) | EP0368584B1 (ko) |
KR (1) | KR0144461B1 (ko) |
DE (1) | DE68927871T2 (ko) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5071792A (en) * | 1990-11-05 | 1991-12-10 | Harris Corporation | Process for forming extremely thin integrated circuit dice |
JPH046875A (ja) * | 1990-04-24 | 1992-01-10 | Mitsubishi Materials Corp | シリコンウェーハ |
DE69127582T2 (de) * | 1990-05-18 | 1998-03-26 | Fujitsu Ltd | Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates |
US5238865A (en) * | 1990-09-21 | 1993-08-24 | Nippon Steel Corporation | Process for producing laminated semiconductor substrate |
US5334281A (en) * | 1992-04-30 | 1994-08-02 | International Business Machines Corporation | Method of forming thin silicon mesas having uniform thickness |
US5234846A (en) * | 1992-04-30 | 1993-08-10 | International Business Machines Corporation | Method of making bipolar transistor with reduced topography |
US5258318A (en) * | 1992-05-15 | 1993-11-02 | International Business Machines Corporation | Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon |
US5324687A (en) * | 1992-10-16 | 1994-06-28 | General Electric Company | Method for thinning of integrated circuit chips for lightweight packaged electronic systems |
US5264395A (en) * | 1992-12-16 | 1993-11-23 | International Business Machines Corporation | Thin SOI layer for fully depleted field effect transistors |
US5436173A (en) * | 1993-01-04 | 1995-07-25 | Texas Instruments Incorporated | Method for forming a semiconductor on insulator device |
US5733175A (en) | 1994-04-25 | 1998-03-31 | Leach; Michael A. | Polishing a workpiece using equal velocity at all points overlapping a polisher |
US5607341A (en) | 1994-08-08 | 1997-03-04 | Leach; Michael A. | Method and structure for polishing a wafer during manufacture of integrated circuits |
US5577309A (en) * | 1995-03-01 | 1996-11-26 | Texas Instruments Incorporated | Method for forming electrical contact to the optical coating of an infrared detector |
JP3552427B2 (ja) | 1996-11-18 | 2004-08-11 | 株式会社日立製作所 | 半導体装置の研磨方法 |
DE19840421C2 (de) | 1998-06-22 | 2000-05-31 | Fraunhofer Ges Forschung | Verfahren zur Fertigung von dünnen Substratschichten und eine dafür geeignete Substratanordnung |
JP4316186B2 (ja) * | 2002-04-05 | 2009-08-19 | シャープ株式会社 | 半導体装置及びその製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4139401A (en) * | 1963-12-04 | 1979-02-13 | Rockwell International Corporation | Method of producing electrically isolated semiconductor devices on common crystalline substrate |
US3407479A (en) * | 1965-06-28 | 1968-10-29 | Motorola Inc | Isolation of semiconductor devices |
US3844858A (en) * | 1968-12-31 | 1974-10-29 | Texas Instruments Inc | Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate |
US3623218A (en) * | 1969-01-16 | 1971-11-30 | Signetics Corp | Method for determining depth of lapping of dielectrically isolated integrated circuits |
US3683491A (en) * | 1970-11-12 | 1972-08-15 | Carroll E Nelson | Method for fabricating pinched resistor semiconductor structure |
US3755012A (en) * | 1971-03-19 | 1973-08-28 | Motorola Inc | Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor |
US4501060A (en) * | 1983-01-24 | 1985-02-26 | At&T Bell Laboratories | Dielectrically isolated semiconductor devices |
JPS61154142A (ja) * | 1984-12-27 | 1986-07-12 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS61159738A (ja) * | 1985-01-08 | 1986-07-19 | Oki Electric Ind Co Ltd | 誘電体分離基板の研摩方法 |
JPS6248040A (ja) * | 1985-08-28 | 1987-03-02 | Nec Corp | 絶縁分離基板及びその製造方法 |
US4944836A (en) * | 1985-10-28 | 1990-07-31 | International Business Machines Corporation | Chem-mech polishing method for producing coplanar metal/insulator films on a substrate |
JPS6356936A (ja) * | 1986-08-27 | 1988-03-11 | Nec Corp | 半導体装置の製造方法 |
US4735679A (en) * | 1987-03-30 | 1988-04-05 | International Business Machines Corporation | Method of improving silicon-on-insulator uniformity |
JPS63250838A (ja) * | 1987-04-08 | 1988-10-18 | Oki Electric Ind Co Ltd | 誘電体分離基板の製造方法 |
JPS63299359A (ja) * | 1987-05-29 | 1988-12-06 | Matsushita Electronics Corp | 半導体装置 |
US4874463A (en) * | 1988-12-23 | 1989-10-17 | At&T Bell Laboratories | Integrated circuits from wafers having improved flatness |
-
1989
- 1989-11-06 US US07/432,123 patent/US5051378A/en not_active Expired - Fee Related
- 1989-11-06 DE DE68927871T patent/DE68927871T2/de not_active Expired - Fee Related
- 1989-11-06 EP EP89311454A patent/EP0368584B1/en not_active Expired - Lifetime
- 1989-11-07 KR KR1019890016068A patent/KR0144461B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0144461B1 (ko) | 1998-08-17 |
EP0368584A2 (en) | 1990-05-16 |
DE68927871D1 (de) | 1997-04-24 |
EP0368584A3 (en) | 1993-02-03 |
US5051378A (en) | 1991-09-24 |
EP0368584B1 (en) | 1997-03-19 |
DE68927871T2 (de) | 1997-07-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20020319 Year of fee payment: 5 |
|
LAPS | Lapse due to unpaid annual fee |