KR880004552A - 반도체장치 제조방법 - Google Patents
반도체장치 제조방법Info
- Publication number
- KR880004552A KR880004552A KR1019870010205A KR870010205A KR880004552A KR 880004552 A KR880004552 A KR 880004552A KR 1019870010205 A KR1019870010205 A KR 1019870010205A KR 870010205 A KR870010205 A KR 870010205A KR 880004552 A KR880004552 A KR 880004552A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- device manufacturing
- manufacturing
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Local Oxidation Of Silicon (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21831986 | 1986-09-17 | ||
JP218319 | 1986-09-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880004552A true KR880004552A (ko) | 1988-06-04 |
KR910002455B1 KR910002455B1 (ko) | 1991-04-22 |
Family
ID=16717986
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019870010205A KR910002455B1 (ko) | 1986-09-17 | 1987-09-15 | 반도체장치 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4910169A (ko) |
EP (1) | EP0261846B1 (ko) |
JP (1) | JPS63301548A (ko) |
KR (1) | KR910002455B1 (ko) |
DE (1) | DE3782904T2 (ko) |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6373660A (ja) * | 1986-09-17 | 1988-04-04 | Fujitsu Ltd | 半導体装置 |
JP2659714B2 (ja) * | 1987-07-21 | 1997-09-30 | 株式会社日立製作所 | 半導体集積回路装置 |
JP2816155B2 (ja) * | 1988-07-27 | 1998-10-27 | 株式会社日立製作所 | 半導体集積回路装置 |
US5254872A (en) * | 1989-03-14 | 1993-10-19 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
JPH0727879B2 (ja) * | 1989-03-14 | 1995-03-29 | 株式会社東芝 | 半導体装置の製造方法 |
JP2839579B2 (ja) * | 1989-10-02 | 1998-12-16 | 株式会社東芝 | 半導体装置及びその製造方法 |
JPH03190232A (ja) * | 1989-12-20 | 1991-08-20 | Fujitsu Ltd | 半導体装置の製造方法 |
EP0507881A1 (en) * | 1990-01-04 | 1992-10-14 | International Business Machines Corporation | Semiconductor interconnect structure utilizing a polyimide insulator |
US5141897A (en) * | 1990-03-23 | 1992-08-25 | At&T Bell Laboratories | Method of making integrated circuit interconnection |
US5094981A (en) * | 1990-04-17 | 1992-03-10 | North American Philips Corporation, Signetics Div. | Technique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier material above 550° C. |
US5268329A (en) * | 1990-05-31 | 1993-12-07 | At&T Bell Laboratories | Method of fabricating an integrated circuit interconnection |
EP0459690A1 (en) * | 1990-05-31 | 1991-12-04 | AT&T Corp. | Integrated circuit interconnection |
JP2665568B2 (ja) * | 1990-11-21 | 1997-10-22 | シャープ株式会社 | 半導体装置の製造方法 |
US5274270A (en) * | 1990-12-17 | 1993-12-28 | Nchip, Inc. | Multichip module having SiO2 insulating layer |
US5243222A (en) * | 1991-04-05 | 1993-09-07 | International Business Machines Corporation | Copper alloy metallurgies for VLSI interconnection structures |
US5130274A (en) * | 1991-04-05 | 1992-07-14 | International Business Machines Corporation | Copper alloy metallurgies for VLSI interconnection structures |
JPH05102155A (ja) * | 1991-10-09 | 1993-04-23 | Sony Corp | 銅配線構造体及びその製造方法 |
US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5391517A (en) * | 1993-09-13 | 1995-02-21 | Motorola Inc. | Process for forming copper interconnect structure |
US5747360A (en) * | 1993-09-17 | 1998-05-05 | Applied Materials, Inc. | Method of metalizing a semiconductor wafer |
US5447887A (en) * | 1994-04-01 | 1995-09-05 | Motorola, Inc. | Method for capping copper in semiconductor devices |
US5504041A (en) * | 1994-08-01 | 1996-04-02 | Texas Instruments Incorporated | Conductive exotic-nitride barrier layer for high-dielectric-constant materials |
US6891269B1 (en) * | 1995-07-05 | 2005-05-10 | Fujitsu Limited | Embedded electroconductive layer structure |
US6084302A (en) * | 1995-12-26 | 2000-07-04 | Micron Technologies, Inc. | Barrier layer cladding around copper interconnect lines |
US5744376A (en) * | 1996-04-08 | 1998-04-28 | Chartered Semiconductor Manufacturing Pte, Ltd | Method of manufacturing copper interconnect with top barrier layer |
US6100196A (en) * | 1996-04-08 | 2000-08-08 | Chartered Semiconductor Manufacturing Ltd. | Method of making a copper interconnect with top barrier layer |
US5693563A (en) * | 1996-07-15 | 1997-12-02 | Chartered Semiconductor Manufacturing Pte Ltd. | Etch stop for copper damascene process |
JP3583562B2 (ja) | 1996-10-18 | 2004-11-04 | 株式会社東芝 | 半導体装置 |
US5770517A (en) * | 1997-03-21 | 1998-06-23 | Advanced Micro Devices, Inc. | Semiconductor fabrication employing copper plug formation within a contact area |
US6140237A (en) * | 1997-06-16 | 2000-10-31 | Chartered Semiconductor Manufacturing Ltd. | Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer |
US6872429B1 (en) * | 1997-06-30 | 2005-03-29 | Applied Materials, Inc. | Deposition of tungsten nitride using plasma pretreatment in a chemical vapor deposition chamber |
KR100417725B1 (ko) * | 1997-12-16 | 2004-02-11 | 인피니언 테크놀로지스 아게 | 집적된 전기 회로 및 그 제조 방법 |
US6906421B1 (en) * | 1998-01-14 | 2005-06-14 | Cypress Semiconductor Corporation | Method of forming a low resistivity Ti-containing interconnect and semiconductor device comprising the same |
US6380627B1 (en) * | 1998-06-26 | 2002-04-30 | The Regents Of The University Of California | Low resistance barrier layer for isolating, adhering, and passivating copper metal in semiconductor fabrication |
JP3279532B2 (ja) * | 1998-11-06 | 2002-04-30 | 日本電気株式会社 | 半導体装置の製造方法 |
US6140255A (en) * | 1998-12-15 | 2000-10-31 | Advanced Micro Devices, Inc. | Method for depositing silicon nitride using low temperatures |
US6248665B1 (en) | 1999-07-06 | 2001-06-19 | Taiwan Semiconductor Manufacturing Company | Delamination improvement between Cu and dielectrics for damascene process |
US6159857A (en) * | 1999-07-08 | 2000-12-12 | Taiwan Semiconductor Manufacturing Company | Robust post Cu-CMP IMD process |
JP4554011B2 (ja) * | 1999-08-10 | 2010-09-29 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
US6153935A (en) | 1999-09-30 | 2000-11-28 | International Business Machines Corporation | Dual etch stop/diffusion barrier for damascene interconnects |
US6373137B1 (en) * | 2000-03-21 | 2002-04-16 | Micron Technology, Inc. | Copper interconnect for an integrated circuit and methods for its fabrication |
WO2002037558A1 (en) * | 2000-11-02 | 2002-05-10 | Fujitsu Limited | Semiconductor device and its manufacturing method |
US6977218B2 (en) * | 2003-07-17 | 2005-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating copper interconnects |
US8114787B2 (en) | 2009-02-19 | 2012-02-14 | Empire Technology Development Llc | Integrated circuit nanowires |
RU2494492C1 (ru) * | 2012-06-07 | 2013-09-27 | Общество с ограниченной ответственностью "Компания РМТ" | Способ создания токопроводящих дорожек |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL87258C (ko) * | 1969-01-15 | |||
US4423547A (en) * | 1981-06-01 | 1984-01-03 | International Business Machines Corporation | Method for forming dense multilevel interconnection metallurgy for semiconductor devices |
EP0074605B1 (en) * | 1981-09-11 | 1990-08-29 | Kabushiki Kaisha Toshiba | Method for manufacturing multilayer circuit substrate |
US4393096A (en) * | 1981-11-16 | 1983-07-12 | International Business Machines Corporation | Aluminum-copper alloy evaporated films with low via resistance |
US4386116A (en) * | 1981-12-24 | 1983-05-31 | International Business Machines Corporation | Process for making multilayer integrated circuit substrate |
US4502207A (en) * | 1982-12-21 | 1985-03-05 | Toshiba Shibaura Denki Kabushiki Kaisha | Wiring material for semiconductor device and method for forming wiring pattern therewith |
US4612698A (en) * | 1984-10-31 | 1986-09-23 | Mobil Solar Energy Corporation | Method of fabricating solar cells |
US4557037A (en) * | 1984-10-31 | 1985-12-10 | Mobil Solar Energy Corporation | Method of fabricating solar cells |
US4609565A (en) * | 1984-10-10 | 1986-09-02 | Mobil Solar Energy Corporation | Method of fabricating solar cells |
US4519872A (en) * | 1984-06-11 | 1985-05-28 | International Business Machines Corporation | Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes |
-
1987
- 1987-09-11 DE DE8787308051T patent/DE3782904T2/de not_active Expired - Fee Related
- 1987-09-11 EP EP87308051A patent/EP0261846B1/en not_active Expired - Lifetime
- 1987-09-15 KR KR1019870010205A patent/KR910002455B1/ko not_active IP Right Cessation
- 1987-09-16 JP JP62231839A patent/JPS63301548A/ja active Granted
- 1987-09-17 US US07/097,739 patent/US4910169A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0261846A1 (en) | 1988-03-30 |
US4910169A (en) | 1990-03-20 |
EP0261846B1 (en) | 1992-12-02 |
JPS63301548A (ja) | 1988-12-08 |
JPH0587173B2 (ko) | 1993-12-15 |
DE3782904D1 (de) | 1993-01-14 |
DE3782904T2 (de) | 1993-04-08 |
KR910002455B1 (ko) | 1991-04-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20020418 Year of fee payment: 12 |
|
LAPS | Lapse due to unpaid annual fee |