KR860006844A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법

Info

Publication number
KR860006844A
KR860006844A KR1019860000674A KR860000674A KR860006844A KR 860006844 A KR860006844 A KR 860006844A KR 1019860000674 A KR1019860000674 A KR 1019860000674A KR 860000674 A KR860000674 A KR 860000674A KR 860006844 A KR860006844 A KR 860006844A
Authority
KR
South Korea
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Application number
KR1019860000674A
Other languages
English (en)
Other versions
KR890004962B1 (ko
Inventor
오구라 미쯔기
쇼지 아리이즈미
후지오 마수오까
Original Assignee
가부시끼가이샤 도오시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60022941A external-priority patent/JPS61183953A/ja
Priority claimed from JP60022942A external-priority patent/JPS61183954A/ja
Priority claimed from JP60022943A external-priority patent/JPS61183967A/ja
Application filed by 가부시끼가이샤 도오시바 filed Critical 가부시끼가이샤 도오시바
Publication of KR860006844A publication Critical patent/KR860006844A/ko
Application granted granted Critical
Publication of KR890004962B1 publication Critical patent/KR890004962B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
KR1019860000674A 1985-02-08 1986-01-31 반도체장치 및 그 제조방법 KR890004962B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP60022941A JPS61183953A (ja) 1985-02-08 1985-02-08 読み出し専用半導体記憶装置
JP60-22943 1985-02-08
JP60022942A JPS61183954A (ja) 1985-02-08 1985-02-08 読み出し専用半導体記憶装置の製造方法
JP60022943A JPS61183967A (ja) 1985-02-08 1985-02-08 半導体装置の製造方法
JP60-22942 1985-02-08
JP60-22941 1985-02-08

Publications (2)

Publication Number Publication Date
KR860006844A true KR860006844A (ko) 1986-09-15
KR890004962B1 KR890004962B1 (ko) 1989-12-02

Family

ID=27284036

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860000674A KR890004962B1 (ko) 1985-02-08 1986-01-31 반도체장치 및 그 제조방법

Country Status (4)

Country Link
US (1) US4992389A (ko)
EP (1) EP0190928B1 (ko)
KR (1) KR890004962B1 (ko)
DE (1) DE3681934D1 (ko)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
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US5227319A (en) * 1985-02-08 1993-07-13 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
JP3059442B2 (ja) 1988-11-09 2000-07-04 株式会社日立製作所 半導体記憶装置
US5472891A (en) * 1986-05-26 1995-12-05 Hitachi, Ltd. Method of manufacturing a semiconductor device
KR920000077B1 (ko) * 1987-07-28 1992-01-06 가부시키가이샤 도시바 반도체장치의 제조방법
US4935380A (en) * 1987-08-04 1990-06-19 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US5247197A (en) * 1987-11-05 1993-09-21 Fujitsu Limited Dynamic random access memory device having improved contact hole structures
US4868138A (en) * 1988-03-23 1989-09-19 Sgs-Thomson Microelectronics, Inc. Method for forming a self-aligned source/drain contact for an MOS transistor
JPH0828473B2 (ja) * 1988-09-29 1996-03-21 三菱電機株式会社 半導体装置およびその製造方法
KR950000141B1 (ko) * 1990-04-03 1995-01-10 미쓰비시 뎅끼 가부시끼가이샤 반도체 장치 및 그 제조방법
DE59009067D1 (de) * 1990-04-27 1995-06-14 Siemens Ag Verfahren zur Herstellung einer Öffnung in einem Halbleiterschichtaufbau und dessen Verwendung zur Herstellung von Kontaktlöchern.
JPH0442579A (ja) * 1990-06-08 1992-02-13 Seiko Epson Corp 薄膜トランジスタ及び製造方法
KR100307272B1 (ko) * 1990-12-04 2002-05-01 하라 레이노스케 Mos소자제조방법
US5066606A (en) * 1990-12-07 1991-11-19 Micron Technology, Inc. Implant method for advanced stacked capacitors
KR950013785B1 (ko) * 1991-01-21 1995-11-16 미쓰비시 뎅끼 가부시끼가이샤 Mos형 전계효과 트랜지스터를 포함하는 반도체장치 및 그 제조방법
EP0549055A3 (en) * 1991-12-23 1996-10-23 Koninkl Philips Electronics Nv Method of manufacturing a semiconductor device provided with a field effect transistor, and such a semiconductor device
SG71664A1 (en) * 1992-04-29 2000-04-18 Siemens Ag Method for the production of a contact hole to a doped region
US5291435A (en) * 1993-01-07 1994-03-01 Yu Shih Chiang Read-only memory cell
US5401987A (en) * 1993-12-01 1995-03-28 Imp, Inc. Self-cascoding CMOS device
US5786247A (en) * 1994-05-06 1998-07-28 Vlsi Technology, Inc. Low voltage CMOS process with individually adjustable LDD spacers
US5471416A (en) * 1994-11-14 1995-11-28 National Semiconductor Corporation Method of programming a CMOS read only memory at the second metal layer in a two-metal process
JPH08255907A (ja) * 1995-01-18 1996-10-01 Canon Inc 絶縁ゲート型トランジスタ及びその製造方法
US5514610A (en) * 1995-03-17 1996-05-07 Taiwan Semiconductor Manufacturing Company Method of making an optimized code ion implantation procedure for read only memory devices
ATE183335T1 (de) * 1995-05-23 1999-08-15 Siemens Ag Halbleiteranordnung mit selbstjustierten kontakten und verfahren zu ihrer herstellung
US5773346A (en) * 1995-12-06 1998-06-30 Micron Technology, Inc. Semiconductor processing method of forming a buried contact
KR100198634B1 (ko) * 1996-09-07 1999-06-15 구본준 반도체 소자의 배선구조 및 제조방법
US5907779A (en) * 1996-10-15 1999-05-25 Samsung Electronics Co., Ltd. Selective landing pad fabricating methods for integrated circuits
JP3436462B2 (ja) * 1996-11-01 2003-08-11 三菱電機株式会社 半導体装置
JP3641103B2 (ja) * 1997-06-27 2005-04-20 株式会社東芝 不揮発性半導体メモリ装置の製造方法
US6200862B1 (en) * 1998-11-06 2001-03-13 Advanced Micro Devices, Inc. Mask for asymmetrical transistor formation with paired transistors
US6754104B2 (en) * 2000-06-22 2004-06-22 Progressant Technologies, Inc. Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3986903A (en) * 1974-03-13 1976-10-19 Intel Corporation Mosfet transistor and method of fabrication
JPS5552262A (en) * 1978-10-12 1980-04-16 Fujitsu Ltd Mos semiconductor device
DE2848978A1 (de) * 1978-11-11 1980-05-22 Bayer Ag Traegerkatalysatoren, ihre herstellung und verwendung
JPS5621372A (en) * 1979-07-31 1981-02-27 Fujitsu Ltd Manufacture of semiconductor device
JPS5626470A (en) * 1979-08-13 1981-03-14 Hitachi Ltd Field-effect transistor manufacturing process
US4376947A (en) * 1979-09-04 1983-03-15 Texas Instruments Incorporated Electrically programmable floating gate semiconductor memory device
DE2947350A1 (de) * 1979-11-23 1981-05-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von mnos-speichertransistoren mit sehr kurzer kanallaenge in silizium-gate-technologie
JPS56130970A (en) * 1980-03-17 1981-10-14 Oki Electric Ind Co Ltd Manufacture of semiconductor device
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
US4330931A (en) * 1981-02-03 1982-05-25 Intel Corporation Process for forming metal plated regions and lines in MOS circuits
US4382827A (en) * 1981-04-27 1983-05-10 Ncr Corporation Silicon nitride S/D ion implant mask in CMOS device fabrication
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
JPS59188974A (ja) * 1983-04-11 1984-10-26 Nec Corp 半導体装置の製造方法
JPS59201461A (ja) * 1983-04-28 1984-11-15 Toshiba Corp 読み出し専用半導体記憶装置およびその製造方法
US4513494A (en) * 1983-07-19 1985-04-30 American Microsystems, Incorporated Late mask process for programming read only memories
US4478679A (en) * 1983-11-30 1984-10-23 Storage Technology Partners Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors
JPS615580A (ja) * 1984-06-19 1986-01-11 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US4992389A (en) 1991-02-12
EP0190928B1 (en) 1991-10-16
EP0190928A2 (en) 1986-08-13
DE3681934D1 (de) 1991-11-21
KR890004962B1 (ko) 1989-12-02
EP0190928A3 (en) 1987-08-19

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A201 Request for examination
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