DE3782904D1 - Verfahren zur ausbildung einer kupfer enthaltenden metallisierungsschicht auf der oberflaeche eines halbleiterbauelementes. - Google Patents

Verfahren zur ausbildung einer kupfer enthaltenden metallisierungsschicht auf der oberflaeche eines halbleiterbauelementes.

Info

Publication number
DE3782904D1
DE3782904D1 DE8787308051T DE3782904T DE3782904D1 DE 3782904 D1 DE3782904 D1 DE 3782904D1 DE 8787308051 T DE8787308051 T DE 8787308051T DE 3782904 T DE3782904 T DE 3782904T DE 3782904 D1 DE3782904 D1 DE 3782904D1
Authority
DE
Germany
Prior art keywords
forming
layer containing
semiconductor component
containing copper
metalizing layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787308051T
Other languages
English (en)
Other versions
DE3782904T2 (de
Inventor
Kazuhiro Hoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3782904D1 publication Critical patent/DE3782904D1/de
Publication of DE3782904T2 publication Critical patent/DE3782904T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Local Oxidation Of Silicon (AREA)
DE8787308051T 1986-09-17 1987-09-11 Verfahren zur ausbildung einer kupfer enthaltenden metallisierungsschicht auf der oberflaeche eines halbleiterbauelementes. Expired - Fee Related DE3782904T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21831986 1986-09-17

Publications (2)

Publication Number Publication Date
DE3782904D1 true DE3782904D1 (de) 1993-01-14
DE3782904T2 DE3782904T2 (de) 1993-04-08

Family

ID=16717986

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787308051T Expired - Fee Related DE3782904T2 (de) 1986-09-17 1987-09-11 Verfahren zur ausbildung einer kupfer enthaltenden metallisierungsschicht auf der oberflaeche eines halbleiterbauelementes.

Country Status (5)

Country Link
US (1) US4910169A (de)
EP (1) EP0261846B1 (de)
JP (1) JPS63301548A (de)
KR (1) KR910002455B1 (de)
DE (1) DE3782904T2 (de)

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JPS6373660A (ja) * 1986-09-17 1988-04-04 Fujitsu Ltd 半導体装置
JP2659714B2 (ja) * 1987-07-21 1997-09-30 株式会社日立製作所 半導体集積回路装置
JP2816155B2 (ja) * 1988-07-27 1998-10-27 株式会社日立製作所 半導体集積回路装置
US5254872A (en) * 1989-03-14 1993-10-19 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JPH0727879B2 (ja) * 1989-03-14 1995-03-29 株式会社東芝 半導体装置の製造方法
JP2839579B2 (ja) * 1989-10-02 1998-12-16 株式会社東芝 半導体装置及びその製造方法
JPH03190232A (ja) * 1989-12-20 1991-08-20 Fujitsu Ltd 半導体装置の製造方法
JPH05504446A (ja) * 1990-01-04 1993-07-08 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン ポリイミド絶縁材を用いた半導体相互接続構造
US5141897A (en) * 1990-03-23 1992-08-25 At&T Bell Laboratories Method of making integrated circuit interconnection
US5094981A (en) * 1990-04-17 1992-03-10 North American Philips Corporation, Signetics Div. Technique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier material above 550° C.
EP0459690A1 (de) * 1990-05-31 1991-12-04 AT&T Corp. Verbindung einer integrierten Schaltung
US5268329A (en) * 1990-05-31 1993-12-07 At&T Bell Laboratories Method of fabricating an integrated circuit interconnection
JP2665568B2 (ja) * 1990-11-21 1997-10-22 シャープ株式会社 半導体装置の製造方法
US5274270A (en) * 1990-12-17 1993-12-28 Nchip, Inc. Multichip module having SiO2 insulating layer
US5130274A (en) * 1991-04-05 1992-07-14 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
US5243222A (en) * 1991-04-05 1993-09-07 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
JPH05102155A (ja) * 1991-10-09 1993-04-23 Sony Corp 銅配線構造体及びその製造方法
US5300813A (en) 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5747360A (en) * 1993-09-17 1998-05-05 Applied Materials, Inc. Method of metalizing a semiconductor wafer
US5447887A (en) * 1994-04-01 1995-09-05 Motorola, Inc. Method for capping copper in semiconductor devices
US5504041A (en) * 1994-08-01 1996-04-02 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant materials
US6891269B1 (en) * 1995-07-05 2005-05-10 Fujitsu Limited Embedded electroconductive layer structure
US6084302A (en) * 1995-12-26 2000-07-04 Micron Technologies, Inc. Barrier layer cladding around copper interconnect lines
US6100196A (en) * 1996-04-08 2000-08-08 Chartered Semiconductor Manufacturing Ltd. Method of making a copper interconnect with top barrier layer
US5744376A (en) * 1996-04-08 1998-04-28 Chartered Semiconductor Manufacturing Pte, Ltd Method of manufacturing copper interconnect with top barrier layer
US5693563A (en) * 1996-07-15 1997-12-02 Chartered Semiconductor Manufacturing Pte Ltd. Etch stop for copper damascene process
JP3583562B2 (ja) 1996-10-18 2004-11-04 株式会社東芝 半導体装置
US5770517A (en) * 1997-03-21 1998-06-23 Advanced Micro Devices, Inc. Semiconductor fabrication employing copper plug formation within a contact area
US6140237A (en) * 1997-06-16 2000-10-31 Chartered Semiconductor Manufacturing Ltd. Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer
US6872429B1 (en) * 1997-06-30 2005-03-29 Applied Materials, Inc. Deposition of tungsten nitride using plasma pretreatment in a chemical vapor deposition chamber
EP1042793A1 (de) 1997-12-16 2000-10-11 Infineon Technologies AG Barriereschicht für kupfermetallisierung
US6906421B1 (en) * 1998-01-14 2005-06-14 Cypress Semiconductor Corporation Method of forming a low resistivity Ti-containing interconnect and semiconductor device comprising the same
US6380627B1 (en) * 1998-06-26 2002-04-30 The Regents Of The University Of California Low resistance barrier layer for isolating, adhering, and passivating copper metal in semiconductor fabrication
JP3279532B2 (ja) * 1998-11-06 2002-04-30 日本電気株式会社 半導体装置の製造方法
US6140255A (en) * 1998-12-15 2000-10-31 Advanced Micro Devices, Inc. Method for depositing silicon nitride using low temperatures
US6248665B1 (en) 1999-07-06 2001-06-19 Taiwan Semiconductor Manufacturing Company Delamination improvement between Cu and dielectrics for damascene process
US6159857A (en) * 1999-07-08 2000-12-12 Taiwan Semiconductor Manufacturing Company Robust post Cu-CMP IMD process
JP4554011B2 (ja) * 1999-08-10 2010-09-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US6153935A (en) 1999-09-30 2000-11-28 International Business Machines Corporation Dual etch stop/diffusion barrier for damascene interconnects
US6373137B1 (en) 2000-03-21 2002-04-16 Micron Technology, Inc. Copper interconnect for an integrated circuit and methods for its fabrication
EP1331664A4 (de) * 2000-11-02 2008-10-08 Fujitsu Ltd Halbleiterbauelement und verfahren zu seiner herstellung
US6977218B2 (en) * 2003-07-17 2005-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating copper interconnects
US8114787B2 (en) * 2009-02-19 2012-02-14 Empire Technology Development Llc Integrated circuit nanowires
RU2494492C1 (ru) * 2012-06-07 2013-09-27 Общество с ограниченной ответственностью "Компания РМТ" Способ создания токопроводящих дорожек

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DE3280233D1 (de) * 1981-09-11 1990-10-04 Toshiba Kawasaki Kk Verfahren zum herstellen eines substrats fuer multischichtschaltung.
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Also Published As

Publication number Publication date
DE3782904T2 (de) 1993-04-08
EP0261846B1 (de) 1992-12-02
JPH0587173B2 (de) 1993-12-15
KR880004552A (ko) 1988-06-04
EP0261846A1 (de) 1988-03-30
JPS63301548A (ja) 1988-12-08
KR910002455B1 (ko) 1991-04-22
US4910169A (en) 1990-03-20

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee