IT7922195A0 - Processo perfezionato per la fabbricazione di dispositivi semiconduttori. - Google Patents

Processo perfezionato per la fabbricazione di dispositivi semiconduttori.

Info

Publication number
IT7922195A0
IT7922195A0 IT7922195A IT2219579A IT7922195A0 IT 7922195 A0 IT7922195 A0 IT 7922195A0 IT 7922195 A IT7922195 A IT 7922195A IT 2219579 A IT2219579 A IT 2219579A IT 7922195 A0 IT7922195 A0 IT 7922195A0
Authority
IT
Italy
Prior art keywords
semiconductor devices
improved process
manufacturing semiconductor
manufacturing
improved
Prior art date
Application number
IT7922195A
Other languages
English (en)
Other versions
IT1165446B (it
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT7922195A0 publication Critical patent/IT7922195A0/it
Application granted granted Critical
Publication of IT1165446B publication Critical patent/IT1165446B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/901—Masterslice integrated circuits comprising bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/923—Active solid-state devices, e.g. transistors, solid-state diodes with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT22195/79A 1978-05-25 1979-04-27 Processo perfezionato per la fabbricazione di dispositivi semiconduttori IT1165446B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/909,605 US4249193A (en) 1978-05-25 1978-05-25 LSI Semiconductor device and fabrication thereof

Publications (2)

Publication Number Publication Date
IT7922195A0 true IT7922195A0 (it) 1979-04-27
IT1165446B IT1165446B (it) 1987-04-22

Family

ID=25427538

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22195/79A IT1165446B (it) 1978-05-25 1979-04-27 Processo perfezionato per la fabbricazione di dispositivi semiconduttori

Country Status (6)

Country Link
US (1) US4249193A (it)
EP (1) EP0005723B1 (it)
JP (1) JPS54154290A (it)
CA (1) CA1120606A (it)
DE (1) DE2963058D1 (it)
IT (1) IT1165446B (it)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295149A (en) * 1978-12-29 1981-10-13 International Business Machines Corporation Master image chip organization technique or method
US4425574A (en) 1979-06-29 1984-01-10 International Business Machines Corporation Buried injector memory cell formed from vertical complementary bipolar transistor circuits and method of fabrication therefor
JPS5775438A (en) * 1980-10-29 1982-05-12 Toshiba Corp Semiconductor element
US4402044A (en) * 1980-11-24 1983-08-30 Texas Instruments Incorporated Microprocessor with strip layout of busses, ALU and registers
JPS57211248A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
DE3276284D1 (en) * 1981-09-10 1987-06-11 Fujitsu Ltd Semiconductor integrated circuit comprising a semiconductor substrate and interconnecting layers
JPS5844743A (ja) * 1981-09-10 1983-03-15 Fujitsu Ltd 半導体集積回路
JPS5884445A (ja) * 1981-11-16 1983-05-20 Hitachi Ltd 大規模集積回路
JPS5890758A (ja) * 1981-11-25 1983-05-30 Mitsubishi Electric Corp 相補形集積回路装置
FR2524206B1 (fr) * 1982-03-26 1985-12-13 Thomson Csf Mat Tel Circuit integre prediffuse, et procede d'interconnexion des cellules de ce circuit
US4511914A (en) * 1982-07-01 1985-04-16 Motorola, Inc. Power bus routing for providing noise isolation in gate arrays
JPS5961944A (ja) * 1982-09-30 1984-04-09 Fujitsu Ltd マスタスライス集積回路の製造方法
EP0119059B1 (en) * 1983-03-09 1988-10-05 Kabushiki Kaisha Toshiba Semiconductor integrated circuit with gate-array arrangement
US4615010A (en) * 1983-06-27 1986-09-30 International Business Machines Corporation Field effect transistor (FET) cascode current switch (FCCS)
US4607339A (en) * 1983-06-27 1986-08-19 International Business Machines Corporation Differential cascode current switch (DCCS) master slice for high efficiency/custom density physical design
US4608649A (en) * 1983-06-27 1986-08-26 International Business Machines Corporation Differential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical design
US4862231A (en) * 1983-11-18 1989-08-29 Harris Corporation Non-contact I/O signal transmission in integrated circuit packaging
US4623911A (en) 1983-12-16 1986-11-18 Rca Corporation High circuit density ICs
DE3584102D1 (de) * 1984-03-08 1991-10-24 Toshiba Kawasaki Kk Integrierte halbleiterschaltungsvorrichtung.
JPH073864B2 (ja) * 1984-06-12 1995-01-18 日本電気株式会社 半導体装置
DE3482528D1 (de) * 1984-06-19 1990-07-19 Siemens Ag In c-mos-technik realisierte basiszelle.
JPH0691156B2 (ja) * 1984-08-09 1994-11-14 日本電気株式会社 半導体集積回路の製造方法
JPH0644593B2 (ja) * 1984-11-09 1994-06-08 株式会社東芝 半導体集積回路装置
US4774559A (en) * 1984-12-03 1988-09-27 International Business Machines Corporation Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring nets
US4845052A (en) * 1986-02-07 1989-07-04 Harris Corporation Method of packaging a non-contact I/O signal transmission integrated circuit
US4760289A (en) * 1986-08-04 1988-07-26 International Business Machines Corporation Two-level differential cascode current switch masterslice
US4931946A (en) * 1988-03-10 1990-06-05 Cirrus Logic, Inc. Programmable tiles
US5021856A (en) * 1989-03-15 1991-06-04 Plessey Overseas Limited Universal cell for bipolar NPN and PNP transistors and resistive elements
JPH04340252A (ja) * 1990-07-27 1992-11-26 Mitsubishi Electric Corp 半導体集積回路装置及びセルの配置配線方法
US5703617A (en) * 1993-10-18 1997-12-30 Crystal Semiconductor Signal driver circuit for liquid crystal displays
JPH09139471A (ja) * 1995-09-07 1997-05-27 Hewlett Packard Co <Hp> オンサーキット・アレイ・プロービング用の補助パッド
US5858817A (en) * 1996-10-10 1999-01-12 Lockheed Martin Corporation Process to personalize master slice wafers and fabricate high density VLSI components with a single masking step
CN114442996B (zh) * 2020-10-30 2025-05-20 深圳比特微电子科技有限公司 计算芯片和算力板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3312871A (en) * 1964-12-23 1967-04-04 Ibm Interconnection arrangement for integrated circuits
CA1024661A (en) * 1974-06-26 1978-01-17 International Business Machines Corporation Wireable planar integrated circuit chip structure
US3999214A (en) * 1974-06-26 1976-12-21 Ibm Corporation Wireable planar integrated circuit chip structure
JPS51117588A (en) * 1975-04-09 1976-10-15 Fujitsu Ltd Manufacturing method of semiconductor equipment
US4032962A (en) * 1975-12-29 1977-06-28 Ibm Corporation High density semiconductor integrated circuit layout
DE2643482A1 (de) * 1976-09-27 1978-03-30 Siemens Ag Halbleiterplaettchen zur herstellung hochintegrierter bausteine
CA1102009A (en) * 1977-09-06 1981-05-26 Algirdas J. Gruodis Integrated circuit layout utilizing separated active circuit and wiring regions

Also Published As

Publication number Publication date
EP0005723A1 (de) 1979-12-12
IT1165446B (it) 1987-04-22
CA1120606A (en) 1982-03-23
JPS54154290A (en) 1979-12-05
US4249193A (en) 1981-02-03
DE2963058D1 (en) 1982-07-29
EP0005723B1 (de) 1982-06-09

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19940428