IT8523417A0 - Procedimento per la valutazione dei parametri di processo nella fabbricazione di dispositivi a semiconduttore. - Google Patents

Procedimento per la valutazione dei parametri di processo nella fabbricazione di dispositivi a semiconduttore.

Info

Publication number
IT8523417A0
IT8523417A0 IT8523417A IT2341785A IT8523417A0 IT 8523417 A0 IT8523417 A0 IT 8523417A0 IT 8523417 A IT8523417 A IT 8523417A IT 2341785 A IT2341785 A IT 2341785A IT 8523417 A0 IT8523417 A0 IT 8523417A0
Authority
IT
Italy
Prior art keywords
evaluation
procedure
manufacture
semiconductor devices
process parameters
Prior art date
Application number
IT8523417A
Other languages
English (en)
Other versions
IT1186523B (it
Inventor
Giuseppe Vento
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT23417/85A priority Critical patent/IT1186523B/it
Publication of IT8523417A0 publication Critical patent/IT8523417A0/it
Priority to NL8603277A priority patent/NL8603277A/nl
Priority to US06/946,239 priority patent/US4782288A/en
Priority to DE3644458A priority patent/DE3644458C2/de
Application granted granted Critical
Publication of IT1186523B publication Critical patent/IT1186523B/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R17/00—Measuring arrangements involving comparison with a reference value, e.g. bridge
    • G01R17/02—Arrangements in which the value to be measured is automatically compared with a reference value

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
IT23417/85A 1985-12-31 1985-12-31 Procedimento per la valutazione dei parametri di processo nella fabbricazione di dispositivi a semiconduttore IT1186523B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT23417/85A IT1186523B (it) 1985-12-31 1985-12-31 Procedimento per la valutazione dei parametri di processo nella fabbricazione di dispositivi a semiconduttore
NL8603277A NL8603277A (nl) 1985-12-31 1986-12-23 Werkwijze voor het evalueren van bewerkingsparameters bij de vervaardiging van halfgeleiderinrichtingen.
US06/946,239 US4782288A (en) 1985-12-31 1986-12-24 Method for evaluating processing parameters in the manufacture of semiconductor devices
DE3644458A DE3644458C2 (de) 1985-12-31 1986-12-24 Verfahren zum Auswerten der Prozeßparameter bei der Herstellung von Halbleiteranordnungen sowie Anordnungen dafür

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT23417/85A IT1186523B (it) 1985-12-31 1985-12-31 Procedimento per la valutazione dei parametri di processo nella fabbricazione di dispositivi a semiconduttore

Publications (2)

Publication Number Publication Date
IT8523417A0 true IT8523417A0 (it) 1985-12-31
IT1186523B IT1186523B (it) 1987-11-26

Family

ID=11206905

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23417/85A IT1186523B (it) 1985-12-31 1985-12-31 Procedimento per la valutazione dei parametri di processo nella fabbricazione di dispositivi a semiconduttore

Country Status (4)

Country Link
US (1) US4782288A (it)
DE (1) DE3644458C2 (it)
IT (1) IT1186523B (it)
NL (1) NL8603277A (it)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043988A (en) * 1989-08-25 1991-08-27 Mcnc Method and apparatus for high precision weighted random pattern generation
US6005406A (en) * 1995-12-07 1999-12-21 International Business Machines Corporation Test device and method facilitating aggressive circuit design
JP3363082B2 (ja) * 1997-12-05 2003-01-07 株式会社東芝 パターンの合わせずれの電気的測定方法
US6429667B1 (en) * 2000-06-19 2002-08-06 International Business Machines Corporation Electrically testable process window monitor for lithographic processing
US6462818B1 (en) 2000-06-22 2002-10-08 Kla-Tencor Corporation Overlay alignment mark design
US7068833B1 (en) * 2000-08-30 2006-06-27 Kla-Tencor Corporation Overlay marks, methods of overlay mark design and methods of overlay measurements
US7541201B2 (en) 2000-08-30 2009-06-02 Kla-Tencor Technologies Corporation Apparatus and methods for determining overlay of structures having rotational or mirror symmetry
US6486954B1 (en) 2000-09-01 2002-11-26 Kla-Tencor Technologies Corporation Overlay alignment measurement mark
US7804994B2 (en) * 2002-02-15 2010-09-28 Kla-Tencor Technologies Corporation Overlay metrology and control method
US7075639B2 (en) * 2003-04-25 2006-07-11 Kla-Tencor Technologies Corporation Method and mark for metrology of phase errors on phase shift masks
US7346878B1 (en) 2003-07-02 2008-03-18 Kla-Tencor Technologies Corporation Apparatus and methods for providing in-chip microtargets for metrology or inspection
US7608468B1 (en) * 2003-07-02 2009-10-27 Kla-Tencor Technologies, Corp. Apparatus and methods for determining overlay and uses of same
US7557921B1 (en) 2005-01-14 2009-07-07 Kla-Tencor Technologies Corporation Apparatus and methods for optically monitoring the fidelity of patterns produced by photolitographic tools
CN101506973A (zh) * 2006-08-17 2009-08-12 Nxp股份有限公司 蚀刻步骤期间对电极的正确钻蚀的测试
US9927718B2 (en) 2010-08-03 2018-03-27 Kla-Tencor Corporation Multi-layer overlay metrology target and complimentary overlay metrology measurement systems
US10890436B2 (en) 2011-07-19 2021-01-12 Kla Corporation Overlay targets with orthogonal underlayer dummyfill
US10078107B2 (en) * 2015-10-27 2018-09-18 Globalfoundries Inc. Wafer level electrical test for optical proximity correction and/or etch bias
US10451412B2 (en) 2016-04-22 2019-10-22 Kla-Tencor Corporation Apparatus and methods for detecting overlay errors using scatterometry

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2473789A1 (fr) * 1980-01-09 1981-07-17 Ibm France Procedes et structures de test pour circuits integres a semi-conducteurs permettant la determination electrique de certaines tolerances lors des etapes photolithographiques.
JPS5789220A (en) * 1980-11-25 1982-06-03 Hitachi Ltd Positioning method and marking for positioning
US4399205A (en) * 1981-11-30 1983-08-16 International Business Machines Corporation Method and apparatus for determining photomask alignment
US4538105A (en) * 1981-12-07 1985-08-27 The Perkin-Elmer Corporation Overlay test wafer
US4516071A (en) * 1982-07-26 1985-05-07 The United States Of America As Represented By The Administration Of The United States National Aeronautics And Space Administration Split-cross-bridge resistor for testing for proper fabrication of integrated circuits
JPS5948924A (ja) * 1982-09-14 1984-03-21 Nec Corp 電子線露光用位置合せマ−ク
US4475811A (en) * 1983-04-28 1984-10-09 The Perkin-Elmer Corporation Overlay test measurement systems
JPS59232416A (ja) * 1983-06-16 1984-12-27 Oki Electric Ind Co Ltd アライメントマ−ク

Also Published As

Publication number Publication date
DE3644458A1 (de) 1987-07-02
DE3644458C2 (de) 1996-05-30
US4782288A (en) 1988-11-01
IT1186523B (it) 1987-11-26
NL8603277A (nl) 1987-07-16

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961227