DE68909090T2 - Diffusionsbarrierenstruktur für eine Halbleitervorrichtung. - Google Patents

Diffusionsbarrierenstruktur für eine Halbleitervorrichtung.

Info

Publication number
DE68909090T2
DE68909090T2 DE89106792T DE68909090T DE68909090T2 DE 68909090 T2 DE68909090 T2 DE 68909090T2 DE 89106792 T DE89106792 T DE 89106792T DE 68909090 T DE68909090 T DE 68909090T DE 68909090 T2 DE68909090 T2 DE 68909090T2
Authority
DE
Germany
Prior art keywords
semiconductor device
diffusion barrier
barrier structure
diffusion
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89106792T
Other languages
English (en)
Other versions
DE68909090D1 (de
Inventor
Kenji Nishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE68909090D1 publication Critical patent/DE68909090D1/de
Publication of DE68909090T2 publication Critical patent/DE68909090T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE89106792T 1988-04-20 1989-04-18 Diffusionsbarrierenstruktur für eine Halbleitervorrichtung. Expired - Fee Related DE68909090T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9776288 1988-04-20

Publications (2)

Publication Number Publication Date
DE68909090D1 DE68909090D1 (de) 1993-10-21
DE68909090T2 true DE68909090T2 (de) 1994-01-13

Family

ID=14200881

Family Applications (1)

Application Number Title Priority Date Filing Date
DE89106792T Expired - Fee Related DE68909090T2 (de) 1988-04-20 1989-04-18 Diffusionsbarrierenstruktur für eine Halbleitervorrichtung.

Country Status (4)

Country Link
US (1) US4990997A (de)
EP (1) EP0338467B1 (de)
KR (1) KR920007783B1 (de)
DE (1) DE68909090T2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0256557B1 (de) * 1986-08-19 1993-01-07 Fujitsu Limited Halbleiteranordnung mit einer Dünnschicht-Verdrahtung und Verfahren zum Herstellen derselben
US5175608A (en) * 1987-06-30 1992-12-29 Hitachi, Ltd. Method of and apparatus for sputtering, and integrated circuit device
US4998157A (en) * 1988-08-06 1991-03-05 Seiko Epson Corporation Ohmic contact to silicon substrate
JPH07109829B2 (ja) * 1989-11-20 1995-11-22 三菱電機株式会社 半導体装置の製造方法
KR930002672B1 (ko) * 1990-06-29 1993-04-07 삼성전자 주식회사 비정질 질화티타늄막을 이용한 금속배선 형성방법
KR920005242A (ko) * 1990-08-20 1992-03-28 김광호 게이트-절연체-반도체의 구조를 가지는 트랜지스터의 제조방법
US5136362A (en) * 1990-11-27 1992-08-04 Grief Malcolm K Electrical contact with diffusion barrier
KR100214036B1 (ko) * 1991-02-19 1999-08-02 이데이 노부유끼 알루미늄계 배선형성방법
DE69209724T2 (de) * 1991-04-29 1996-10-10 Philips Electronics Nv Erhöhung der Diffusionsbarriere einer Metallisierungsstruktur geeignet zur Herstellung von Halbleiterbauelementen
JPH05109715A (ja) * 1991-10-16 1993-04-30 Nec Corp 半導体装置の製造方法
US5231306A (en) * 1992-01-31 1993-07-27 Micron Technology, Inc. Titanium/aluminum/nitrogen material for semiconductor devices
US5723382A (en) * 1992-06-12 1998-03-03 Sandhu; Gurtej S. Method of making a low-resistance contact to silicon having a titanium silicide interface, an amorphous titanium nitride barrier layer and a conductive plug
US6081034A (en) 1992-06-12 2000-06-27 Micron Technology, Inc. Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer
JP3201061B2 (ja) * 1993-03-05 2001-08-20 ソニー株式会社 配線構造の製造方法
US5604140A (en) * 1995-05-22 1997-02-18 Lg Semicon, Co. Ltd. Method for forming fine titanium nitride film and method for fabricating semiconductor element using the same
US5736192A (en) * 1995-07-05 1998-04-07 Fujitsu Limited Embedded electroconductive layer and method for formation thereof
US6891269B1 (en) * 1995-07-05 2005-05-10 Fujitsu Limited Embedded electroconductive layer structure
KR100243286B1 (ko) * 1997-03-05 2000-03-02 윤종용 반도체 장치의 제조방법
GB2324882B (en) * 1997-04-29 2001-05-23 Daewoo Electronics Co Ltd Array of thin film actuated mirrors and method for the manufacture thereof
KR19990003495A (ko) * 1997-06-25 1999-01-15 김영환 반도체 소자의 베리어 금속층 형성방법
US6156647A (en) * 1997-10-27 2000-12-05 Applied Materials, Inc. Barrier layer structure which prevents migration of silicon into an adjacent metallic layer and the method of fabrication of the barrier layer
US6002174A (en) * 1997-12-31 1999-12-14 Micron Technology, Inc. Barrier materials for semiconductor devices
US6331811B2 (en) * 1998-06-12 2001-12-18 Nec Corporation Thin-film resistor, wiring substrate, and method for manufacturing the same
US6236113B1 (en) * 1999-03-05 2001-05-22 Sharp Laboratories Of America, Inc. Iridium composite barrier structure and method for same
JP3473485B2 (ja) * 1999-04-08 2003-12-02 日本電気株式会社 薄膜抵抗体およびその製造方法
US6498397B1 (en) * 2000-11-06 2002-12-24 Advanced Micro Devices, Inc. Seed layer with annealed region for integrated circuit interconnects
KR100543655B1 (ko) * 2003-06-30 2006-01-20 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR100917823B1 (ko) * 2007-12-28 2009-09-18 주식회사 동부하이텍 반도체 소자의 금속 배선 형성 방법
US20160104669A1 (en) * 2014-10-08 2016-04-14 Infineon Technologies Ag Semiconductor structure with improved metallization adhesion and method for manufacturing the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066465A (ja) * 1983-09-21 1985-04-16 Seiko Epson Corp 半導体装置
JPS60119755A (ja) * 1983-12-01 1985-06-27 Nec Corp 多層配線半導体集積回路装置
US4829363A (en) * 1984-04-13 1989-05-09 Fairchild Camera And Instrument Corp. Structure for inhibiting dopant out-diffusion
JPS61156872A (ja) * 1984-12-28 1986-07-16 Fujitsu Ltd 半導体装置
JPS61256766A (ja) * 1985-05-10 1986-11-14 Hitachi Ltd 化合物半導体用電極
US4702967A (en) * 1986-06-16 1987-10-27 Harris Corporation Multiple-layer, multiple-phase titanium/nitrogen adhesion/diffusion barrier layer structure for gold-base microcircuit interconnection

Also Published As

Publication number Publication date
KR890016655A (ko) 1989-11-29
KR920007783B1 (ko) 1992-09-17
DE68909090D1 (de) 1993-10-21
EP0338467A1 (de) 1989-10-25
EP0338467B1 (de) 1993-09-15
US4990997A (en) 1991-02-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee