DE602007009001D1 - Prüfverfahren für eine Halbleiterspeichervorrichtung und Halbleiterspeichervorrichtung dafür - Google Patents

Prüfverfahren für eine Halbleiterspeichervorrichtung und Halbleiterspeichervorrichtung dafür

Info

Publication number
DE602007009001D1
DE602007009001D1 DE602007009001T DE602007009001T DE602007009001D1 DE 602007009001 D1 DE602007009001 D1 DE 602007009001D1 DE 602007009001 T DE602007009001 T DE 602007009001T DE 602007009001 T DE602007009001 T DE 602007009001T DE 602007009001 D1 DE602007009001 D1 DE 602007009001D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
test method
therefor
device therefor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007009001T
Other languages
English (en)
Inventor
Hiroyoshi Tomita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of DE602007009001D1 publication Critical patent/DE602007009001D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
DE602007009001T 2006-08-31 2007-08-29 Prüfverfahren für eine Halbleiterspeichervorrichtung und Halbleiterspeichervorrichtung dafür Active DE602007009001D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006235750A JP5114894B2 (ja) 2006-08-31 2006-08-31 半導体記憶装置の試験方法及びその半導体記憶装置

Publications (1)

Publication Number Publication Date
DE602007009001D1 true DE602007009001D1 (de) 2010-10-21

Family

ID=38786937

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007009001T Active DE602007009001D1 (de) 2006-08-31 2007-08-29 Prüfverfahren für eine Halbleiterspeichervorrichtung und Halbleiterspeichervorrichtung dafür

Country Status (6)

Country Link
US (1) US7633818B2 (de)
EP (1) EP1898427B1 (de)
JP (1) JP5114894B2 (de)
KR (1) KR100918469B1 (de)
CN (1) CN101136253B (de)
DE (1) DE602007009001D1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100878315B1 (ko) * 2007-08-14 2009-01-14 주식회사 하이닉스반도체 반도체 집적회로
JP2009245497A (ja) * 2008-03-31 2009-10-22 Elpida Memory Inc 半導体記憶装置及びその不良検出方法
JP5673935B2 (ja) * 2010-12-28 2015-02-18 セイコーエプソン株式会社 不揮発性記憶装置、電子機器
CN104751900B (zh) * 2013-12-31 2017-10-17 北京兆易创新科技股份有限公司 一种或非型闪存中存储单元间串扰的测试方法
KR20160107979A (ko) * 2015-03-06 2016-09-19 에스케이하이닉스 주식회사 메모리 장치
US9412461B1 (en) * 2015-03-10 2016-08-09 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US20180150233A1 (en) * 2015-06-03 2018-05-31 Hitachi, Ltd. Storage system
JP6886850B2 (ja) * 2017-04-04 2021-06-16 ラピスセミコンダクタ株式会社 半導体記憶装置および半導体記憶装置の試験方法
EP4231301A4 (de) 2020-09-18 2024-06-19 Changxin Memory Tech Inc Bitleitungsabtastschaltung und speicher
CN114203247B (zh) * 2020-09-18 2024-03-26 长鑫存储技术有限公司 一种位线感测电路及存储器
US11967356B2 (en) 2021-06-17 2024-04-23 Micron Technology, Inc. Concurrent compensation in a memory system
US11942171B2 (en) * 2021-12-29 2024-03-26 Micron Technology, Inc. Concurrent compensation in a memory system
CN114333961B (zh) * 2022-01-10 2023-09-05 长鑫存储技术有限公司 存储器阵列的测试方法、装置、设备及存储介质
CN116844616A (zh) * 2022-03-23 2023-10-03 长鑫存储技术有限公司 感应放大器感应边界确定方法及装置、介质及设备
US11978504B2 (en) 2022-03-23 2024-05-07 Changxin Memory Technologies, Inc. Method and apparatus for determining sense boundary of sense amplifier, medium, and device
US11798617B2 (en) 2022-03-23 2023-10-24 Changxin Memory Technologies, Inc. Method and apparatus for determining sense boundary of sense amplifier, medium, and device
CN116844618A (zh) 2022-03-23 2023-10-03 长鑫存储技术有限公司 存储器测试方法及装置、介质及设备
CN114566202B (zh) * 2022-04-26 2022-08-02 长鑫存储技术有限公司 一种感测放大器的测试方法、装置、存储装置及存储系统
CN117174153A (zh) * 2022-05-25 2023-12-05 长鑫存储技术有限公司 感应放大器感应边界检测方法与电子设备

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH041999A (ja) 1990-04-17 1992-01-07 Mitsubishi Electric Corp 半導体ダイナミツクｒａｍ
JP3549602B2 (ja) * 1995-01-12 2004-08-04 株式会社ルネサステクノロジ 半導体記憶装置
JPH09120682A (ja) * 1995-10-24 1997-05-06 Mitsubishi Electric Corp 半導体メモリ装置
JP3175665B2 (ja) * 1997-10-24 2001-06-11 日本電気株式会社 不揮発性半導体記憶装置のデータ消去方法
EP0947994A3 (de) * 1998-03-30 2004-02-18 Siemens Aktiengesellschaft Reduziertessignalprüfung für dynamischen Direktzugriffspeicher
JP2001067898A (ja) * 1999-08-30 2001-03-16 Mitsubishi Electric Corp 半導体記憶装置
JP4707244B2 (ja) * 2000-03-30 2011-06-22 ルネサスエレクトロニクス株式会社 半導体記憶装置および半導体装置
JP2002074992A (ja) * 2000-09-01 2002-03-15 Mitsubishi Electric Corp 半導体記憶装置
JP2002093165A (ja) * 2000-09-18 2002-03-29 Mitsubishi Electric Corp 半導体記憶装置
JP2002117670A (ja) * 2000-10-04 2002-04-19 Mitsubishi Electric Corp 半導体記憶装置
JP2002208298A (ja) * 2001-01-10 2002-07-26 Mitsubishi Electric Corp 半導体記憶装置
JP2004145931A (ja) 2002-10-22 2004-05-20 Renesas Technology Corp 半導体記憶装置
JP4370100B2 (ja) * 2003-01-10 2009-11-25 パナソニック株式会社 半導体記憶装置
JP4137060B2 (ja) * 2003-03-06 2008-08-20 富士通株式会社 半導体メモリおよびダイナミックメモリセルの電荷蓄積方法

Also Published As

Publication number Publication date
EP1898427B1 (de) 2010-09-08
US20080056032A1 (en) 2008-03-06
JP5114894B2 (ja) 2013-01-09
JP2008059687A (ja) 2008-03-13
KR20080021530A (ko) 2008-03-07
CN101136253B (zh) 2010-12-08
CN101136253A (zh) 2008-03-05
EP1898427A3 (de) 2008-05-28
KR100918469B1 (ko) 2009-09-24
US7633818B2 (en) 2009-12-15
EP1898427A2 (de) 2008-03-12

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