DE602006012797D1 - Testschaltung und Testverfahren für ein Halbleiterbauelement und Halbleiterchip - Google Patents

Testschaltung und Testverfahren für ein Halbleiterbauelement und Halbleiterchip

Info

Publication number
DE602006012797D1
DE602006012797D1 DE602006012797T DE602006012797T DE602006012797D1 DE 602006012797 D1 DE602006012797 D1 DE 602006012797D1 DE 602006012797 T DE602006012797 T DE 602006012797T DE 602006012797 T DE602006012797 T DE 602006012797T DE 602006012797 D1 DE602006012797 D1 DE 602006012797D1
Authority
DE
Germany
Prior art keywords
test
semiconductor device
semiconductor chip
test method
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006012797T
Other languages
English (en)
Inventor
Hidetoshi Sugiyama
Masao Nakajima
Haruyuki Mouri
Hideaki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of DE602006012797D1 publication Critical patent/DE602006012797D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31721—Power aspects, e.g. power supplies for test circuits, power saving during test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE602006012797T 2006-02-28 2006-06-29 Testschaltung und Testverfahren für ein Halbleiterbauelement und Halbleiterchip Active DE602006012797D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006054033A JP4861022B2 (ja) 2006-02-28 2006-02-28 半導体装置の試験用回路および試験方法、半導体ウエハ、並びに半導体チップの製造方法

Publications (1)

Publication Number Publication Date
DE602006012797D1 true DE602006012797D1 (de) 2010-04-22

Family

ID=38191341

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006012797T Active DE602006012797D1 (de) 2006-02-28 2006-06-29 Testschaltung und Testverfahren für ein Halbleiterbauelement und Halbleiterchip

Country Status (6)

Country Link
US (1) US7603248B2 (de)
EP (1) EP1826580B1 (de)
JP (1) JP4861022B2 (de)
KR (1) KR100801529B1 (de)
CN (1) CN100585827C (de)
DE (1) DE602006012797D1 (de)

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JP2006245063A (ja) * 2005-02-28 2006-09-14 Nec Electronics Corp 半導体チップおよび半導体チップを搭載する半導体装置
KR100951572B1 (ko) * 2007-12-26 2010-04-09 주식회사 하이닉스반도체 테스트 진입 회로와 테스트 진입 신호 생성 방법
JP2009265024A (ja) * 2008-04-28 2009-11-12 Nec Electronics Corp 半導体装置
US7885129B2 (en) * 2008-05-28 2011-02-08 Macronix International Co., Ltd Memory chip and method for operating the same
JP5565767B2 (ja) * 2009-07-28 2014-08-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR101218606B1 (ko) * 2011-02-28 2013-01-04 에스케이하이닉스 주식회사 반도체 메모리 장치
FR2973564A1 (fr) 2011-04-01 2012-10-05 St Microelectronics Rousset Securisation d'une plaquette de circuits electroniques
FR2973562A1 (fr) * 2011-04-01 2012-10-05 St Microelectronics Rousset Communication sans contact avec une plaquette de circuits electroniques
US8627158B2 (en) 2011-12-08 2014-01-07 International Business Machines Corporation Flash array built in self test engine with trace array and flash metric reporting
CN102543960A (zh) * 2012-02-10 2012-07-04 上海宏力半导体制造有限公司 一种测试用集成电路
CN102946329B (zh) * 2012-11-08 2015-07-08 成都华太航空科技有限公司 曼切斯特编码收发机测试台
US9607191B1 (en) * 2014-06-12 2017-03-28 Impinj, Inc. RFID tag memory check using wireless margin read commands
KR20170016636A (ko) * 2015-08-04 2017-02-14 에스케이하이닉스 주식회사 파라미터 설정 회로, 반도체 장치 및 이를 이용한 반도체 시스템
US10345338B2 (en) * 2015-09-21 2019-07-09 Biosense Webster (Israel ) LTD. Test cap for a cable
CN106847726A (zh) * 2017-02-08 2017-06-13 上海华虹宏力半导体制造有限公司 晶圆测试方法
CN108494389A (zh) * 2018-05-03 2018-09-04 杭州百隆电子有限公司 一种编码修调电路及修调方法
KR102553267B1 (ko) * 2018-05-17 2023-07-07 삼성전자 주식회사 멀티-채널 패키지, 및 그 패키지를 테스트하는 테스트 장치 및 테스트 방법
CN110457172B (zh) * 2019-08-12 2023-09-29 兆讯恒达科技股份有限公司 一种用于流片过程中的检测方法
CN113224034B (zh) * 2020-01-21 2022-05-17 厦门凌阳华芯科技有限公司 一种晶圆及光掩膜版
KR20220111577A (ko) * 2021-02-02 2022-08-09 에스케이하이닉스 주식회사 메모리 장치 및 그 동작 방법

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US4446475A (en) 1981-07-10 1984-05-01 Motorola, Inc. Means and method for disabling access to a memory
US4845351A (en) 1985-09-30 1989-07-04 Casio Computer Co., Ltd. IC card
JPS6428863A (en) * 1987-07-23 1989-01-31 Mitsubishi Electric Corp Semiconductor wafer
US5059899A (en) 1990-08-16 1991-10-22 Micron Technology, Inc. Semiconductor dies and wafers and methods for making
US5206181A (en) * 1991-06-03 1993-04-27 Motorola, Inc. Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing
JPH05299484A (ja) * 1992-04-20 1993-11-12 Sumitomo Electric Ind Ltd 半導体ウェハ
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
JP2716399B2 (ja) 1995-04-27 1998-02-18 日本電気アイシーマイコンシステム株式会社 半導体集積回路装置
JP3734853B2 (ja) * 1995-06-27 2006-01-11 株式会社ルネサステクノロジ 半導体記憶装置
JP3529581B2 (ja) * 1997-03-14 2004-05-24 東芝マイクロエレクトロニクス株式会社 半導体ウェーハ及びｉｃカード
US5899703A (en) 1997-03-28 1999-05-04 International Business Machines Corporation Method for chip testing
JP3383551B2 (ja) * 1997-07-03 2003-03-04 株式会社東芝 半導体装置及びその製造方法
JP2001135597A (ja) * 1999-08-26 2001-05-18 Fujitsu Ltd 半導体装置の製造方法
JP2001291751A (ja) * 2000-04-06 2001-10-19 Sony Corp 半導体装置
JP2002176140A (ja) * 2000-12-06 2002-06-21 Seiko Epson Corp 半導体集積回路ウェハ
DE10146177C2 (de) 2001-09-19 2003-12-11 Infineon Technologies Ag Wafer mit zusätzlichen Schaltungsteilen im Kerfbereich zum Testen von integrierten Schaltungen auf dem Wafer
JP2003124275A (ja) 2001-10-12 2003-04-25 Toshiba Corp 半導体ウェーハ
US7035753B2 (en) * 2002-03-20 2006-04-25 Infineon Technologies Ag Method and apparatus for placing an integrated circuit into a default mode of operation
JP2004111539A (ja) * 2002-09-17 2004-04-08 Matsushita Electric Ind Co Ltd 半導体装置、及びその検査方法
US6815973B1 (en) * 2003-06-13 2004-11-09 Xilinx, Inc. Optical testing port and wafer level testing without probe cards
DE102004014644A1 (de) 2004-03-25 2005-10-13 Atmel Germany Gmbh Integrierter Schaltkreis

Also Published As

Publication number Publication date
CN101030547A (zh) 2007-09-05
US20070203662A1 (en) 2007-08-30
US7603248B2 (en) 2009-10-13
KR20070089561A (ko) 2007-08-31
JP2007234833A (ja) 2007-09-13
EP1826580A2 (de) 2007-08-29
EP1826580B1 (de) 2010-03-10
JP4861022B2 (ja) 2012-01-25
EP1826580A3 (de) 2008-03-19
KR100801529B1 (ko) 2008-02-12
CN100585827C (zh) 2010-01-27

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE

8364 No opposition during term of opposition