DE602007000219D1 - Nichtflüchtige Speichervorrichtung und Betriebsverfahren dafür - Google Patents

Nichtflüchtige Speichervorrichtung und Betriebsverfahren dafür

Info

Publication number
DE602007000219D1
DE602007000219D1 DE602007000219T DE602007000219T DE602007000219D1 DE 602007000219 D1 DE602007000219 D1 DE 602007000219D1 DE 602007000219 T DE602007000219 T DE 602007000219T DE 602007000219 T DE602007000219 T DE 602007000219T DE 602007000219 D1 DE602007000219 D1 DE 602007000219D1
Authority
DE
Germany
Prior art keywords
memory device
volatile memory
operating method
method therefor
therefor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007000219T
Other languages
English (en)
Inventor
Dae-Yong Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE602007000219D1 publication Critical patent/DE602007000219D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
DE602007000219T 2006-02-17 2007-02-16 Nichtflüchtige Speichervorrichtung und Betriebsverfahren dafür Active DE602007000219D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060015821A KR100771517B1 (ko) 2006-02-17 2006-02-17 칩 사이즈를 줄일 수 있는 플래시 메모리 장치
US11/653,866 US7733695B2 (en) 2006-02-17 2007-01-17 Non-volatile memory device and method of operation therefor

Publications (1)

Publication Number Publication Date
DE602007000219D1 true DE602007000219D1 (de) 2008-12-18

Family

ID=38428022

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007000219T Active DE602007000219D1 (de) 2006-02-17 2007-02-16 Nichtflüchtige Speichervorrichtung und Betriebsverfahren dafür

Country Status (4)

Country Link
US (3) US7733695B2 (de)
KR (1) KR100771517B1 (de)
CN (1) CN101038922B (de)
DE (1) DE602007000219D1 (de)

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KR100771517B1 (ko) * 2006-02-17 2007-10-30 삼성전자주식회사 칩 사이즈를 줄일 수 있는 플래시 메모리 장치
KR101053745B1 (ko) * 2009-05-29 2011-08-02 주식회사 하이닉스반도체 비트라인 프리차지 회로 및 이를 포함하는 불휘발성 메모리 장치
JP5377131B2 (ja) 2009-07-17 2013-12-25 株式会社東芝 半導体記憶装置
DE102009041935B3 (de) * 2009-09-17 2011-04-14 Austriamicrosystems Ag Schaltungsanordnung mit einem Zustandsspeicherelement und Verfahren zum Betreiben eines Zustandsspeicherelements
KR20110044501A (ko) * 2009-10-23 2011-04-29 삼성전자주식회사 개선된 레이아웃 마진을 갖는 반도체 모듈 및 그에 따른 신호라인 레이아웃 방법
JP2011119530A (ja) 2009-12-04 2011-06-16 Toshiba Corp 半導体記憶装置
KR101936911B1 (ko) * 2011-05-31 2019-01-11 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 이를 포함하는 반도체 집적 회로 장치
JP5550609B2 (ja) 2011-07-13 2014-07-16 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
TWI459390B (zh) * 2011-09-26 2014-11-01 Winbond Electronics Corp 半導體記憶裝置
CN103035293B (zh) * 2011-10-08 2015-07-15 华邦电子股份有限公司 半导体存储装置
JP5626812B2 (ja) * 2012-08-30 2014-11-19 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
JP5868889B2 (ja) * 2013-03-25 2016-02-24 株式会社東芝 不揮発性半導体記憶装置
JP6103664B1 (ja) * 2016-02-18 2017-03-29 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
US10339989B2 (en) * 2016-11-17 2019-07-02 Samsung Electronics Co., Ltd. Page buffer, a memory device including the same and a read operation method thereof
KR20200130573A (ko) * 2019-05-09 2020-11-19 삼성전자주식회사 불휘발성 메모리 장치, 그것의 동작 방법, 및 불휘발성 메모리 장치를 포함하는 스토리지 시스템

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KR0139951B1 (ko) 1995-06-08 1998-06-01 곽원천 버섯종균 자동접종장치
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KR100445794B1 (ko) * 1997-12-26 2004-10-14 삼성전자주식회사 노어형 플래시 메모리 장치의 소거 방법
KR100316060B1 (ko) * 1998-06-16 2002-02-19 박종섭 플래시메모리의레이아웃및그형성방법
JP3660503B2 (ja) 1998-07-28 2005-06-15 株式会社東芝 不揮発性半導体記憶装置
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JP2000294658A (ja) 1999-04-02 2000-10-20 Matsushita Electronics Industry Corp 不揮発性半導体記憶装置及びその駆動方法
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JP3863330B2 (ja) * 1999-09-28 2006-12-27 株式会社東芝 不揮発性半導体メモリ
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KR100591122B1 (ko) * 2003-12-26 2006-06-19 동부일렉트로닉스 주식회사 플래시메모리, 그의 구동방법 및 그의 배치구조
JP2005197308A (ja) * 2003-12-26 2005-07-21 Toshiba Corp 不揮発性半導体記憶装置
EP1569242A1 (de) * 2004-02-27 2005-08-31 STMicroelectronics S.r.l. Elektrisch wort-löschbare nicht-flüchtige Speicheranordnung und dazugehöriges Vorspannungsverfahren
KR100630535B1 (ko) * 2004-03-23 2006-09-29 에스티마이크로일렉트로닉스 엔.브이. 멀티 레벨 낸드 플래시 메모리 셀의 독출 방법 및 회로
JP2006004514A (ja) * 2004-06-17 2006-01-05 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR20060002337A (ko) * 2004-07-01 2006-01-09 삼성전자주식회사 부분 소노스 게이트를 갖는 플래시메모리 셀의 구동 방법
JP4768256B2 (ja) * 2004-12-16 2011-09-07 株式会社東芝 半導体記憶装置
KR100771517B1 (ko) * 2006-02-17 2007-10-30 삼성전자주식회사 칩 사이즈를 줄일 수 있는 플래시 메모리 장치

Also Published As

Publication number Publication date
US8081509B2 (en) 2011-12-20
US20120014187A1 (en) 2012-01-19
KR20070082764A (ko) 2007-08-22
CN101038922A (zh) 2007-09-19
US20070195609A1 (en) 2007-08-23
KR100771517B1 (ko) 2007-10-30
US8339851B2 (en) 2012-12-25
US20100208526A1 (en) 2010-08-19
CN101038922B (zh) 2010-09-29
US7733695B2 (en) 2010-06-08

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