DE602007009007D1 - Halbleiterspeicher und -system - Google Patents

Halbleiterspeicher und -system

Info

Publication number
DE602007009007D1
DE602007009007D1 DE602007009007T DE602007009007T DE602007009007D1 DE 602007009007 D1 DE602007009007 D1 DE 602007009007D1 DE 602007009007 T DE602007009007 T DE 602007009007T DE 602007009007 T DE602007009007 T DE 602007009007T DE 602007009007 D1 DE602007009007 D1 DE 602007009007D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007009007T
Other languages
English (en)
Inventor
Hiroyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of DE602007009007D1 publication Critical patent/DE602007009007D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4065—Low level details of refresh operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE602007009007T 2006-09-27 2007-08-29 Halbleiterspeicher und -system Active DE602007009007D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006262757A JP5151106B2 (ja) 2006-09-27 2006-09-27 半導体メモリおよびシステム

Publications (1)

Publication Number Publication Date
DE602007009007D1 true DE602007009007D1 (de) 2010-10-21

Family

ID=38896890

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007009007T Active DE602007009007D1 (de) 2006-09-27 2007-08-29 Halbleiterspeicher und -system

Country Status (6)

Country Link
US (1) US7564736B2 (de)
EP (1) EP1906409B1 (de)
JP (1) JP5151106B2 (de)
KR (1) KR100992470B1 (de)
CN (1) CN101154435B (de)
DE (1) DE602007009007D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4962206B2 (ja) * 2007-08-10 2012-06-27 富士通セミコンダクター株式会社 半導体記憶装置及びワードデコーダ制御方法
KR100968155B1 (ko) * 2008-10-02 2010-07-06 주식회사 하이닉스반도체 반도체 메모리 장치
JP5343544B2 (ja) * 2008-12-08 2013-11-13 富士通セミコンダクター株式会社 半導体メモリ、半導体装置およびシステム
US8400866B2 (en) * 2009-08-06 2013-03-19 Magsil Corporation Voltage boosting in MRAM current drivers
CN102081964B (zh) * 2009-11-30 2014-12-10 国际商业机器公司 动态随机访问存储器刷新的方法和系统
US8588022B2 (en) 2011-08-24 2013-11-19 Micron Technology, Inc. Memory refresh methods, memory section control circuits, and apparatuses
US9196330B2 (en) * 2012-01-17 2015-11-24 Qualcomm Incorporated Mimicking multi-voltage domain wordline decoding logic for a memory array
US20150243346A1 (en) * 2012-09-26 2015-08-27 Ps4 Luxco S.A.R.L. Semiconductor device having hierarchically structured word lines
KR102130171B1 (ko) * 2014-01-13 2020-07-03 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
CN107104665B (zh) * 2016-02-19 2020-08-28 中芯国际集成电路制造(上海)有限公司 电平转换电路
US10659045B2 (en) 2017-06-27 2020-05-19 Silicon Laboratories Inc. Apparatus with electronic circuitry having reduced leakage current and associated methods
KR102615012B1 (ko) 2018-11-12 2023-12-19 삼성전자주식회사 메모리 장치 및 그것의 동작 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07111084A (ja) * 1993-10-13 1995-04-25 Oki Micro Design Miyazaki:Kk 半導体集積回路装置
KR960011206B1 (ko) * 1993-11-09 1996-08-21 삼성전자 주식회사 반도체메모리장치의 워드라인구동회로
JP3667787B2 (ja) 1994-05-11 2005-07-06 株式会社ルネサステクノロジ 半導体記憶装置
KR0121131B1 (ko) * 1994-10-13 1997-11-10 문정환 반도체 메모리장치의 구동회로
US5701143A (en) * 1995-01-31 1997-12-23 Cirrus Logic, Inc. Circuits, systems and methods for improving row select speed in a row select memory device
JPH10112181A (ja) * 1996-10-08 1998-04-28 Fujitsu Ltd 半導体記憶装置
JP4437710B2 (ja) * 2003-10-30 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体メモリ
WO2006013632A1 (ja) * 2004-08-05 2006-02-09 Fujitsu Limited 半導体メモリ
JP5343544B2 (ja) * 2008-12-08 2013-11-13 富士通セミコンダクター株式会社 半導体メモリ、半導体装置およびシステム

Also Published As

Publication number Publication date
EP1906409B1 (de) 2010-09-08
KR100992470B1 (ko) 2010-11-08
JP5151106B2 (ja) 2013-02-27
US7564736B2 (en) 2009-07-21
CN101154435A (zh) 2008-04-02
EP1906409A2 (de) 2008-04-02
KR20080028799A (ko) 2008-04-01
CN101154435B (zh) 2012-06-27
JP2008084428A (ja) 2008-04-10
EP1906409A3 (de) 2008-09-17
US20080074942A1 (en) 2008-03-27

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Legal Events

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8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE