ITMI20041957A1 - Dispositivo di memoria - Google Patents

Dispositivo di memoria

Info

Publication number
ITMI20041957A1
ITMI20041957A1 IT001957A ITMI20041957A ITMI20041957A1 IT MI20041957 A1 ITMI20041957 A1 IT MI20041957A1 IT 001957 A IT001957 A IT 001957A IT MI20041957 A ITMI20041957 A IT MI20041957A IT MI20041957 A1 ITMI20041957 A1 IT MI20041957A1
Authority
IT
Italy
Prior art keywords
memory device
memory
Prior art date
Application number
IT001957A
Other languages
English (en)
Inventor
Emanuele Confalonieri
Gatto Nicola Del
Carla Giuseppina Poidomani
Marco Sforzin
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT001957A priority Critical patent/ITMI20041957A1/it
Publication of ITMI20041957A1 publication Critical patent/ITMI20041957A1/it
Priority to US11/250,176 priority patent/US7352645B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
IT001957A 2004-10-15 2004-10-15 Dispositivo di memoria ITMI20041957A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT001957A ITMI20041957A1 (it) 2004-10-15 2004-10-15 Dispositivo di memoria
US11/250,176 US7352645B2 (en) 2004-10-15 2005-10-13 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT001957A ITMI20041957A1 (it) 2004-10-15 2004-10-15 Dispositivo di memoria

Publications (1)

Publication Number Publication Date
ITMI20041957A1 true ITMI20041957A1 (it) 2005-01-15

Family

ID=36180586

Family Applications (1)

Application Number Title Priority Date Filing Date
IT001957A ITMI20041957A1 (it) 2004-10-15 2004-10-15 Dispositivo di memoria

Country Status (2)

Country Link
US (1) US7352645B2 (it)
IT (1) ITMI20041957A1 (it)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4519612B2 (ja) * 2004-11-16 2010-08-04 株式会社東芝 不揮発性半導体記憶装置
KR100732633B1 (ko) * 2006-02-01 2007-06-27 삼성전자주식회사 비연속적인 비트라인 디코딩을 수행하는 플래시 메모리장치
US7512032B2 (en) * 2006-03-28 2009-03-31 Andrea Martinelli Electronic device comprising non volatile memory cells with optimized programming and corresponding programming method
JP4504397B2 (ja) * 2007-05-29 2010-07-14 株式会社東芝 半導体記憶装置
KR100901851B1 (ko) * 2007-06-28 2009-06-09 삼성전자주식회사 저항체를 이용한 비휘발성 메모리 장치 및 그 구동 방법
US7733718B2 (en) * 2007-07-04 2010-06-08 Hynix Semiconductor, Inc. One-transistor type DRAM
US7890472B2 (en) * 2007-09-18 2011-02-15 Microsoft Corporation Parallel nested transactions in transactional memory
KR101317754B1 (ko) * 2007-10-12 2013-10-11 삼성전자주식회사 상 변화 메모리 장치
US7692975B2 (en) * 2008-05-09 2010-04-06 Micron Technology, Inc. System and method for mitigating reverse bias leakage
US8004899B2 (en) * 2009-03-05 2011-08-23 Macronix International Co., Ltd. Memory array and method of operating a memory
TWI451420B (zh) * 2010-01-20 2014-09-01 Macronix Int Co Ltd 具有記憶體程式化放電電路之積體電路裝置及其方法
US8593860B2 (en) 2011-12-09 2013-11-26 Gsi Technology, Inc. Systems and methods of sectioned bit line memory arrays
US8693236B2 (en) 2011-12-09 2014-04-08 Gsi Technology, Inc. Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features
US9030886B2 (en) * 2012-12-07 2015-05-12 United Microelectronics Corp. Memory device and driving method thereof
US9019761B1 (en) * 2013-10-18 2015-04-28 Winbond Electronics Corp. Memory device and column decoder for reducing capacitive coupling effect on adjacent memory cells
CN104766619B (zh) * 2014-01-06 2017-07-21 华邦电子股份有限公司 存储器装置和存储器控制方法
JP2019046514A (ja) * 2017-08-29 2019-03-22 東芝メモリ株式会社 半導体記憶装置
US11380387B1 (en) * 2021-03-23 2022-07-05 Micron Technology, Inc. Multiplexor for a semiconductor device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0442495A (ja) * 1990-06-07 1992-02-13 Mitsubishi Electric Corp 半導体記憶装置
JP3210355B2 (ja) * 1991-03-04 2001-09-17 株式会社東芝 不揮発性半導体記憶装置
US5396452A (en) * 1993-07-02 1995-03-07 Wahlstrom; Sven E. Dynamic random access memory
US5814853A (en) 1996-01-22 1998-09-29 Advanced Micro Devices, Inc. Sourceless floating gate memory device and method of storing data
JP2845212B2 (ja) * 1996-08-29 1999-01-13 日本電気株式会社 半導体記憶装置
US6975539B2 (en) 1999-01-14 2005-12-13 Silicon Storage Technology, Inc. Digital multilevel non-volatile memory system
US6175523B1 (en) 1999-10-25 2001-01-16 Advanced Micro Devices, Inc Precharging mechanism and method for NAND-based flash memory devices
US6240020B1 (en) 1999-10-25 2001-05-29 Advanced Micro Devices Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices
DE60041037D1 (de) 2000-03-21 2009-01-22 St Microelectronics Srl Strang-programmierbarer nichtflüchtiger Speicher mit NOR-Architektur
JP2002100196A (ja) 2000-09-26 2002-04-05 Matsushita Electric Ind Co Ltd 半導体記憶装置
US6480419B2 (en) 2001-02-22 2002-11-12 Samsung Electronics Co., Ltd. Bit line setup and discharge circuit for programming non-volatile memory
KR100399353B1 (ko) 2001-07-13 2003-09-26 삼성전자주식회사 시분할 감지 기능을 구비한 불 휘발성 반도체 메모리 장치및 그것의 읽기 방법
KR100463195B1 (ko) 2001-08-28 2004-12-23 삼성전자주식회사 가속 열 스캔닝 스킴을 갖는 불 휘발성 반도체 메모리 장치
KR100423894B1 (ko) 2002-05-09 2004-03-22 삼성전자주식회사 저전압 반도체 메모리 장치
JP3833970B2 (ja) 2002-06-07 2006-10-18 株式会社東芝 不揮発性半導体メモリ
US6717839B1 (en) 2003-03-31 2004-04-06 Ramtron International Corporation Bit-line shielding method for ferroelectric memories
TWI246084B (en) * 2004-12-30 2005-12-21 Univ Nat Chiao Tung Method for eliminating crosstalk interference of contact/via-programmed read-only-memory

Also Published As

Publication number Publication date
US20060083078A1 (en) 2006-04-20
US7352645B2 (en) 2008-04-01

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