ITMI20042462A1 - Memoria ausiliare - Google Patents

Memoria ausiliare

Info

Publication number
ITMI20042462A1
ITMI20042462A1 IT002462A ITMI20042462A ITMI20042462A1 IT MI20042462 A1 ITMI20042462 A1 IT MI20042462A1 IT 002462 A IT002462 A IT 002462A IT MI20042462 A ITMI20042462 A IT MI20042462A IT MI20042462 A1 ITMI20042462 A1 IT MI20042462A1
Authority
IT
Italy
Prior art keywords
auxiliary memory
auxiliary
memory
Prior art date
Application number
IT002462A
Other languages
English (en)
Inventor
Federico Pio
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT002462A priority Critical patent/ITMI20042462A1/it
Publication of ITMI20042462A1 publication Critical patent/ITMI20042462A1/it
Priority to US11/318,053 priority patent/US7630263B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
IT002462A 2004-12-23 2004-12-23 Memoria ausiliare ITMI20042462A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT002462A ITMI20042462A1 (it) 2004-12-23 2004-12-23 Memoria ausiliare
US11/318,053 US7630263B2 (en) 2004-12-23 2005-12-23 Exploiting a statistical distribution of the values of an electrical characteristic in a population of auxiliary memory cells for obtaining reference cells

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT002462A ITMI20042462A1 (it) 2004-12-23 2004-12-23 Memoria ausiliare

Publications (1)

Publication Number Publication Date
ITMI20042462A1 true ITMI20042462A1 (it) 2005-03-23

Family

ID=36696585

Family Applications (1)

Application Number Title Priority Date Filing Date
IT002462A ITMI20042462A1 (it) 2004-12-23 2004-12-23 Memoria ausiliare

Country Status (2)

Country Link
US (1) US7630263B2 (it)
IT (1) ITMI20042462A1 (it)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7817475B2 (en) * 2007-12-05 2010-10-19 Ovonyx, Inc. Method and apparatus for accessing a phase-change memory
US7787282B2 (en) 2008-03-21 2010-08-31 Micron Technology, Inc. Sensing resistance variable memory
US7881100B2 (en) * 2008-04-08 2011-02-01 Micron Technology, Inc. State machine sensing of memory cells
US7660152B2 (en) * 2008-04-30 2010-02-09 International Business Machines Corporation Method and apparatus for implementing self-referencing read operation for PCRAM devices
JP2010055719A (ja) * 2008-08-29 2010-03-11 Toshiba Corp 抵抗変化メモリ装置
JP2010134994A (ja) * 2008-12-04 2010-06-17 Elpida Memory Inc 半導体装置及びそのカリブレーション方法
IT1392921B1 (it) * 2009-02-11 2012-04-02 St Microelectronics Srl Regioni allocabili dinamicamente in memorie non volatili
WO2013114615A1 (ja) * 2012-02-03 2013-08-08 富士通株式会社 半導体集積回路、半導体集積回路の試験方法
US9142311B2 (en) * 2013-06-13 2015-09-22 Cypress Semiconductor Corporation Screening for reference cells in a memory
FR3035536B1 (fr) 2015-04-21 2017-05-12 Commissariat Energie Atomique Procede de determination d'une impulsion de tension optimale pour programmer une cellule memoire flash
US9847117B1 (en) 2016-09-26 2017-12-19 Micron Technology, Inc. Dynamic reference voltage determination
CN113906511A (zh) 2019-05-31 2022-01-07 美光科技公司 非易失性存储器装置中的数据读取与编程的安全性及正确性的改进
US11139025B2 (en) 2020-01-22 2021-10-05 International Business Machines Corporation Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array
US11276473B2 (en) * 2020-08-07 2022-03-15 Micron Technology, Inc. Coarse calibration based on signal and noise characteristics of memory cells collected in prior calibration operations
TWI772237B (zh) 2020-12-18 2022-07-21 力旺電子股份有限公司 記憶體裝置及其操作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7071771B2 (en) * 2000-12-11 2006-07-04 Kabushiki Kaisha Toshiba Current difference divider circuit
US6651032B2 (en) * 2001-03-15 2003-11-18 Intel Corporation Setting data retention thresholds in charge-based memory
JP2004062922A (ja) * 2002-07-25 2004-02-26 Renesas Technology Corp 不揮発性半導体記憶装置
JP4086583B2 (ja) * 2002-08-08 2008-05-14 シャープ株式会社 不揮発性半導体メモリ装置およびデータ書き込み制御方法
JP3914869B2 (ja) * 2002-12-20 2007-05-16 スパンション インク 不揮発性メモリ及びその書き換え方法
JP2004348802A (ja) * 2003-05-20 2004-12-09 Sharp Corp 不揮発性メモリ素子のプログラム検証方法および半導体記憶装置とそれを備えた携帯電子機器
JP4245437B2 (ja) * 2003-08-08 2009-03-25 シャープ株式会社 不揮発性半導体記憶装置の書き込み方法
KR100660534B1 (ko) * 2004-12-09 2006-12-26 삼성전자주식회사 불휘발성 메모리 장치의 프로그램 검증방법

Also Published As

Publication number Publication date
US20060164898A1 (en) 2006-07-27
US7630263B2 (en) 2009-12-08

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