DE602005004508D1 - Speichersystem und Speichersteuerverfahren - Google Patents

Speichersystem und Speichersteuerverfahren

Info

Publication number
DE602005004508D1
DE602005004508D1 DE602005004508T DE602005004508T DE602005004508D1 DE 602005004508 D1 DE602005004508 D1 DE 602005004508D1 DE 602005004508 T DE602005004508 T DE 602005004508T DE 602005004508 T DE602005004508 T DE 602005004508T DE 602005004508 D1 DE602005004508 D1 DE 602005004508D1
Authority
DE
Germany
Prior art keywords
memory
control method
memory system
memory control
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005004508T
Other languages
English (en)
Other versions
DE602005004508T2 (de
Inventor
Nobuyuki Minowa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE602005004508D1 publication Critical patent/DE602005004508D1/de
Application granted granted Critical
Publication of DE602005004508T2 publication Critical patent/DE602005004508T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/067—Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
DE602005004508T 2005-04-01 2005-09-29 Speichersystem und Speichersteuerverfahren Active DE602005004508T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005106613A JP4794194B2 (ja) 2005-04-01 2005-04-01 ストレージシステム及び記憶制御方法
JP2005106613 2005-04-01

Publications (2)

Publication Number Publication Date
DE602005004508D1 true DE602005004508D1 (de) 2008-03-13
DE602005004508T2 DE602005004508T2 (de) 2009-01-29

Family

ID=35840119

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005004508T Active DE602005004508T2 (de) 2005-04-01 2005-09-29 Speichersystem und Speichersteuerverfahren

Country Status (4)

Country Link
US (1) US7395392B2 (de)
EP (1) EP1708076B1 (de)
JP (1) JP4794194B2 (de)
DE (1) DE602005004508T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5057755B2 (ja) * 2006-11-28 2012-10-24 株式会社日立製作所 記憶制御装置及びその制御方法
JP4369467B2 (ja) 2006-12-12 2009-11-18 富士通株式会社 データ中継装置、ストレージ装置、およびデータ中継方法
JP4475598B2 (ja) * 2007-06-26 2010-06-09 株式会社日立製作所 ストレージシステム及びストレージシステムの制御方法
US8775717B2 (en) * 2007-12-27 2014-07-08 Sandisk Enterprise Ip Llc Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories
JP5102917B2 (ja) * 2008-02-22 2012-12-19 株式会社日立製作所 ストレージ装置及びアクセス命令送信方法
US8527710B2 (en) 2009-02-17 2013-09-03 Hitachi, Ltd. Storage controller and method of controlling storage controller
US8285943B2 (en) 2009-06-18 2012-10-09 Hitachi, Ltd. Storage control apparatus and method of controlling storage control apparatus
US20110153969A1 (en) * 2009-12-18 2011-06-23 William Petrick Device and method to control communications between and access to computer networks, systems or devices
US8489918B2 (en) 2010-04-21 2013-07-16 Hitachi, Ltd. Storage system and ownership control method for storage system
US8412892B2 (en) 2010-04-21 2013-04-02 Hitachi, Ltd. Storage system and ownership control method for storage system
US20140136740A1 (en) * 2011-06-29 2014-05-15 Hitachi, Ltd. Input-output control unit and frame processing method for the input-output control unit
KR20190086177A (ko) * 2018-01-12 2019-07-22 에스케이하이닉스 주식회사 컨트롤러 및 그것의 동작방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0554005A (ja) * 1991-08-23 1993-03-05 Kyocera Corp マルチプロセツサシステム
US5577204A (en) 1993-12-15 1996-11-19 Convex Computer Corporation Parallel processing computer system interconnections utilizing unidirectional communication links with separate request and response lines for direct communication or using a crossbar switching device
JP3772369B2 (ja) * 1995-11-20 2006-05-10 株式会社日立製作所 記憶サブシステム
JP3657428B2 (ja) * 1998-04-27 2005-06-08 株式会社日立製作所 記憶制御装置
JP4123621B2 (ja) * 1999-02-16 2008-07-23 株式会社日立製作所 主記憶共有型マルチプロセッサシステム及びその共有領域設定方法
JP4309508B2 (ja) * 1999-03-25 2009-08-05 コニカミノルタビジネステクノロジーズ株式会社 Ｄｍａ制御装置
JP3769413B2 (ja) * 1999-03-17 2006-04-26 株式会社日立製作所 ディスクアレイ制御装置
JP4053208B2 (ja) * 2000-04-27 2008-02-27 株式会社日立製作所 ディスクアレイ制御装置
JP3426223B2 (ja) * 2000-09-27 2003-07-14 株式会社ソニー・コンピュータエンタテインメント マルチプロセッサシステム、データ処理システム、データ処理方法、コンピュータプログラム
JP2004110503A (ja) 2002-09-19 2004-04-08 Hitachi Ltd 記憶制御装置、記憶システム、記憶制御装置の制御方法、チャネル制御部、及びプログラム
JP4112954B2 (ja) * 2002-11-21 2008-07-02 株式会社日立製作所 磁気ディスク記憶制御装置
US7028147B2 (en) * 2002-12-13 2006-04-11 Sun Microsystems, Inc. System and method for efficiently and reliably performing write cache mirroring
JP2004227098A (ja) 2003-01-20 2004-08-12 Hitachi Ltd 記憶デバイス制御装置の制御方法、及び記憶デバイス制御装置

Also Published As

Publication number Publication date
JP2006285778A (ja) 2006-10-19
EP1708076A1 (de) 2006-10-04
US20060236052A1 (en) 2006-10-19
US7395392B2 (en) 2008-07-01
EP1708076B1 (de) 2008-01-23
JP4794194B2 (ja) 2011-10-19
DE602005004508T2 (de) 2009-01-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition