DE602004015226D1 - Wortleitung Speisespannungsverstärkungsschaltung für DRAM - Google Patents

Wortleitung Speisespannungsverstärkungsschaltung für DRAM

Info

Publication number
DE602004015226D1
DE602004015226D1 DE602004015226T DE602004015226T DE602004015226D1 DE 602004015226 D1 DE602004015226 D1 DE 602004015226D1 DE 602004015226 T DE602004015226 T DE 602004015226T DE 602004015226 T DE602004015226 T DE 602004015226T DE 602004015226 D1 DE602004015226 D1 DE 602004015226D1
Authority
DE
Germany
Prior art keywords
dram
supply voltage
word line
amplification circuit
voltage amplification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004015226T
Other languages
English (en)
Inventor
Hiroyuki Kobayashi
Tatsuya Kanda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE602004015226D1 publication Critical patent/DE602004015226D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE602004015226T 2003-10-30 2004-10-29 Wortleitung Speisespannungsverstärkungsschaltung für DRAM Active DE602004015226D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003370589 2003-10-30
JP2004191947A JP4437710B2 (ja) 2003-10-30 2004-06-29 半導体メモリ

Publications (1)

Publication Number Publication Date
DE602004015226D1 true DE602004015226D1 (de) 2008-09-04

Family

ID=34425412

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004015226T Active DE602004015226D1 (de) 2003-10-30 2004-10-29 Wortleitung Speisespannungsverstärkungsschaltung für DRAM

Country Status (5)

Country Link
US (1) US7184358B2 (de)
EP (1) EP1528572B1 (de)
JP (1) JP4437710B2 (de)
CN (1) CN1612267B (de)
DE (1) DE602004015226D1 (de)

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JP4437710B2 (ja) 2003-10-30 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体メモリ
US20050105372A1 (en) * 2003-10-30 2005-05-19 Fujitsu Limited Semiconductor memory
US7548484B2 (en) * 2005-09-29 2009-06-16 Hynix Semiconductor Inc. Semiconductor memory device having column decoder
JP2007109310A (ja) * 2005-10-13 2007-04-26 Elpida Memory Inc 電源制御回路及びそれを備えた半導体装置
JP2007164922A (ja) * 2005-12-15 2007-06-28 Matsushita Electric Ind Co Ltd デコーダ回路
US8126348B2 (en) * 2006-02-06 2012-02-28 Samsung Electronics Co., Ltd. Printing apparatus to reduce power consumption and control method thereof
JP5224659B2 (ja) * 2006-07-13 2013-07-03 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP4267006B2 (ja) * 2006-07-24 2009-05-27 エルピーダメモリ株式会社 半導体記憶装置
KR100802057B1 (ko) 2006-08-11 2008-02-12 삼성전자주식회사 반도체 메모리 장치의 워드 라인 구동 회로 및 방법
JP5151106B2 (ja) 2006-09-27 2013-02-27 富士通セミコンダクター株式会社 半導体メモリおよびシステム
JP2008135099A (ja) 2006-11-27 2008-06-12 Elpida Memory Inc 半導体記憶装置
US7639066B2 (en) * 2006-12-15 2009-12-29 Qimonda North America Corp. Circuit and method for suppressing gate induced drain leakage
JP4962206B2 (ja) * 2007-08-10 2012-06-27 富士通セミコンダクター株式会社 半導体記憶装置及びワードデコーダ制御方法
JP5202248B2 (ja) * 2008-11-26 2013-06-05 パナソニック株式会社 半導体記憶装置
JP5343544B2 (ja) * 2008-12-08 2013-11-13 富士通セミコンダクター株式会社 半導体メモリ、半導体装置およびシステム
CN101894584B (zh) * 2010-06-12 2013-01-16 苏州国芯科技有限公司 一种动态随机存储器读写模式信号时序参数的实现方法
CN102479545B (zh) * 2010-11-29 2014-08-13 中国科学院微电子研究所 一种6t cmos sram单元
JP2013114700A (ja) * 2011-11-25 2013-06-10 Elpida Memory Inc 半導体装置
US20150243346A1 (en) * 2012-09-26 2015-08-27 Ps4 Luxco S.A.R.L. Semiconductor device having hierarchically structured word lines
CN102867535B (zh) * 2012-09-27 2016-12-21 上海华虹宏力半导体制造有限公司 存储器及其字线电压产生电路
JP6190697B2 (ja) * 2013-11-07 2017-08-30 ルネサスエレクトロニクス株式会社 半導体装置
KR20150136950A (ko) * 2014-05-28 2015-12-08 에스케이하이닉스 주식회사 액티브 드라이버 및 이를 포함하는 반도체 장치
KR101705172B1 (ko) * 2015-01-29 2017-02-09 경북대학교 산학협력단 반도체 메모리 장치
FR3033076B1 (fr) 2015-02-23 2017-12-22 St Microelectronics Rousset Memoire non volatile ayant un decodeur de ligne a polarite variable
ITUB20151112A1 (it) 2015-05-27 2016-11-27 St Microelectronics Srl Dispositivo di memoria non-volatile e corrispondente metodo di funzionamento con riduzione degli stress
KR102615012B1 (ko) 2018-11-12 2023-12-19 삼성전자주식회사 메모리 장치 및 그것의 동작 방법
JP2021127734A (ja) * 2020-02-14 2021-09-02 マツダ株式会社 回転出力装置の制御装置
US11929130B2 (en) 2020-09-30 2024-03-12 Changxin Memory Technologies, Inc. Method and device for testing sr cycle as well as method and device for testing ar number
CN114765039A (zh) * 2021-01-15 2022-07-19 长鑫存储技术有限公司 自刷新频率的检测方法
CN116319154B (zh) * 2023-05-22 2023-08-22 南京芯驰半导体科技有限公司 一种控制电路及can收发器系统

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JPH04259983A (ja) * 1991-02-15 1992-09-16 Hitachi Ltd 半導体記憶装置
JPH07287980A (ja) 1994-04-20 1995-10-31 Mitsubishi Electric Corp 半導体記憶装置の電源電圧発生回路
JP3667787B2 (ja) * 1994-05-11 2005-07-06 株式会社ルネサステクノロジ 半導体記憶装置
JP3645593B2 (ja) * 1994-09-09 2005-05-11 株式会社ルネサステクノロジ 半導体集積回路装置
KR0164814B1 (ko) * 1995-01-23 1999-02-01 김광호 반도체 메모리장치의 전압 구동회로
US5701143A (en) * 1995-01-31 1997-12-23 Cirrus Logic, Inc. Circuits, systems and methods for improving row select speed in a row select memory device
JP4000206B2 (ja) * 1996-08-29 2007-10-31 富士通株式会社 半導体記憶装置
JP2000173263A (ja) * 1998-12-04 2000-06-23 Mitsubishi Electric Corp 半導体記憶装置
JP2001052476A (ja) * 1999-08-05 2001-02-23 Mitsubishi Electric Corp 半導体装置
JP2001126477A (ja) * 1999-10-27 2001-05-11 Mitsubishi Electric Corp 半導体集積回路
US6563746B2 (en) * 1999-11-09 2003-05-13 Fujitsu Limited Circuit for entering/exiting semiconductor memory device into/from low power consumption mode and method of controlling internal circuit at low power consumption mode
US6459650B1 (en) * 2001-05-15 2002-10-01 Jmos Technology, Inc. Method and apparatus for asynchronously controlling a DRAM array in a SRAM environment
JP4152094B2 (ja) 2001-09-03 2008-09-17 エルピーダメモリ株式会社 半導体記憶装置の制御方法及び半導体記憶装置
JP2003109398A (ja) * 2001-09-28 2003-04-11 Mitsubishi Electric Corp 半導体記憶装置
US6512705B1 (en) * 2001-11-21 2003-01-28 Micron Technology, Inc. Method and apparatus for standby power reduction in semiconductor devices
JP2003173675A (ja) * 2001-12-03 2003-06-20 Mitsubishi Electric Corp 半導体集積回路
JP4184104B2 (ja) * 2003-01-30 2008-11-19 株式会社ルネサステクノロジ 半導体装置
JP4437710B2 (ja) 2003-10-30 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体メモリ
US20050105372A1 (en) * 2003-10-30 2005-05-19 Fujitsu Limited Semiconductor memory

Also Published As

Publication number Publication date
US7184358B2 (en) 2007-02-27
CN1612267B (zh) 2010-06-23
US20050105322A1 (en) 2005-05-19
JP2005158223A (ja) 2005-06-16
EP1528572A3 (de) 2006-01-25
JP4437710B2 (ja) 2010-03-24
EP1528572B1 (de) 2008-07-23
EP1528572A2 (de) 2005-05-04
CN1612267A (zh) 2005-05-04

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE