ITMI20051011A1 - Dispositivo di memoria a semiconduttore e procedimento di disposizione di sue linee di segnsle e alimentazione. - Google Patents
Dispositivo di memoria a semiconduttore e procedimento di disposizione di sue linee di segnsle e alimentazione.Info
- Publication number
- ITMI20051011A1 ITMI20051011A1 IT001011A ITMI20051011A ITMI20051011A1 IT MI20051011 A1 ITMI20051011 A1 IT MI20051011A1 IT 001011 A IT001011 A IT 001011A IT MI20051011 A ITMI20051011 A IT MI20051011A IT MI20051011 A1 ITMI20051011 A1 IT MI20051011A1
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- arrangement
- signal
- power supply
- memory device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20040040542 | 2004-06-03 | ||
| KR1020040074730A KR100689814B1 (ko) | 2004-06-03 | 2004-09-17 | 반도체 메모리 장치 및 이 장치의 신호 라인 및 파워 라인배치 방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ITMI20051011A1 true ITMI20051011A1 (it) | 2005-12-04 |
Family
ID=35912557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT001011A ITMI20051011A1 (it) | 2004-06-03 | 2005-05-30 | Dispositivo di memoria a semiconduttore e procedimento di disposizione di sue linee di segnsle e alimentazione. |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR100689814B1 (it) |
| CN (1) | CN100424877C (it) |
| IT (1) | ITMI20051011A1 (it) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7808804B2 (en) | 2006-11-10 | 2010-10-05 | Samsung Electronics Co., Ltd. | Power line layout |
| CN105825881B (zh) * | 2015-01-09 | 2019-01-01 | 旺宏电子股份有限公司 | 记忆体 |
| KR102646847B1 (ko) * | 2016-12-07 | 2024-03-12 | 삼성전자주식회사 | 반도체 메모리 장치, 반도체 메모리 장치의 동작 방법 및 메모리 시스템 |
| US10304497B2 (en) * | 2017-08-17 | 2019-05-28 | Micron Technology, Inc. | Power supply wiring in a semiconductor memory device |
| KR102335107B1 (ko) * | 2017-10-16 | 2021-12-03 | 삼성전자 주식회사 | 로우 디코더를 포함하는 비휘발성 메모리 장치 |
| CN112558669B (zh) * | 2020-12-10 | 2022-05-31 | 无锡中微亿芯有限公司 | 一种fpga的具有自测试可调功能的分布式电源网络 |
| CN114530174B (zh) * | 2022-01-21 | 2024-08-09 | 长江先进存储产业创新中心有限责任公司 | 存储器及存储系统 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100258345B1 (ko) * | 1996-11-28 | 2000-06-01 | 윤종용 | 파워라인의 배치구조를 개선한 반도체 메모리 장치 |
| KR100211768B1 (ko) * | 1996-12-06 | 1999-08-02 | 윤종용 | 삼중 금속층을 가지는 반도체 메모리 장치 |
| JP2000049305A (ja) * | 1998-07-28 | 2000-02-18 | Hitachi Ltd | 半導体記憶装置 |
| KR100655068B1 (ko) * | 2000-09-14 | 2006-12-08 | 삼성전자주식회사 | 셋업/홀드 윈도우 및 스큐를 개선하는 신호라인배치구조를 가지는 반도체 장치 |
| US6664634B2 (en) * | 2001-03-15 | 2003-12-16 | Micron Technology, Inc. | Metal wiring pattern for memory devices |
-
2004
- 2004-09-17 KR KR1020040074730A patent/KR100689814B1/ko active IP Right Grant
-
2005
- 2005-05-30 IT IT001011A patent/ITMI20051011A1/it unknown
- 2005-06-03 CN CNB2005100817846A patent/CN100424877C/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR20050115196A (ko) | 2005-12-07 |
| KR100689814B1 (ko) | 2007-03-08 |
| CN100424877C (zh) | 2008-10-08 |
| CN1722443A (zh) | 2006-01-18 |
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