DE60129104D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE60129104D1
DE60129104D1 DE60129104T DE60129104T DE60129104D1 DE 60129104 D1 DE60129104 D1 DE 60129104D1 DE 60129104 T DE60129104 T DE 60129104T DE 60129104 T DE60129104 T DE 60129104T DE 60129104 D1 DE60129104 D1 DE 60129104D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60129104T
Other languages
English (en)
Other versions
DE60129104T2 (de
Inventor
Yoshimasa Yagishita
Toshiya Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE60129104D1 publication Critical patent/DE60129104D1/de
Application granted granted Critical
Publication of DE60129104T2 publication Critical patent/DE60129104T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
DE60129104T 2001-03-29 2001-12-05 Halbleiterspeicheranordnung Expired - Lifetime DE60129104T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001096344 2001-03-29
JP2001096344A JP3945993B2 (ja) 2001-03-29 2001-03-29 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE60129104D1 true DE60129104D1 (de) 2007-08-09
DE60129104T2 DE60129104T2 (de) 2007-10-25

Family

ID=18950268

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60129104T Expired - Lifetime DE60129104T2 (de) 2001-03-29 2001-12-05 Halbleiterspeicheranordnung

Country Status (7)

Country Link
US (2) US6654298B2 (de)
EP (1) EP1246200B1 (de)
JP (1) JP3945993B2 (de)
KR (1) KR100757760B1 (de)
CN (1) CN100477001C (de)
DE (1) DE60129104T2 (de)
TW (1) TW533429B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1440169A (zh) * 2003-03-12 2003-09-03 富奥汽车零部件有限公司制泵分公司 位置码通讯方法及装置
JP3836804B2 (ja) * 2003-04-02 2006-10-25 株式会社東芝 半導体記憶装置
US9202532B2 (en) 2012-09-13 2015-12-01 Winbond Electronics Corp. Burst sequence control and multi-valued fuse scheme in memory device
US11282558B2 (en) * 2020-05-21 2022-03-22 Wuxi Petabyte Technologies Co., Ltd. Ferroelectric random-access memory with ROMFUSE area having redundant configuration wordlines

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US4666828A (en) * 1984-08-15 1987-05-19 The General Hospital Corporation Test for Huntington's disease
US4683202A (en) * 1985-03-28 1987-07-28 Cetus Corporation Process for amplifying nucleic acid sequences
US4801531A (en) * 1985-04-17 1989-01-31 Biotechnology Research Partners, Ltd. Apo AI/CIII genomic polymorphisms predictive of atherosclerosis
US5617365A (en) * 1988-10-07 1997-04-01 Hitachi, Ltd. Semiconductor device having redundancy circuit
US5272057A (en) * 1988-10-14 1993-12-21 Georgetown University Method of detecting a predisposition to cancer by the use of restriction fragment length polymorphism of the gene for human poly (ADP-ribose) polymerase
US6212089B1 (en) * 1996-03-19 2001-04-03 Hitachi, Ltd. Semiconductor memory device and defect remedying method thereof
US5192659A (en) * 1989-08-25 1993-03-09 Genetype Ag Intron sequence analysis method for detection of adjacent and remote locus alleles as haplotypes
US5612211A (en) * 1990-06-08 1997-03-18 New York University Stimulation, production and culturing of hematopoietic progenitor cells by fibroblast growth factors
US5851832A (en) * 1991-07-08 1998-12-22 Neurospheres, Ltd. In vitro growth and proliferation of multipotent neural stem cells and their progeny
US5446692A (en) * 1992-02-14 1995-08-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having redundancy memory cells shared among memory blocks
JPH0729373A (ja) * 1993-07-08 1995-01-31 Mitsubishi Electric Corp 半導体記憶装置
JPH07254298A (ja) * 1994-03-15 1995-10-03 Fujitsu Ltd 半導体記憶装置
JP2914171B2 (ja) * 1994-04-25 1999-06-28 松下電器産業株式会社 半導体メモリ装置およびその駆動方法
KR0177740B1 (ko) * 1994-11-17 1999-04-15 김광호 반도체 메모리 장치의 리던던시 회로 및 그 방법
KR100247920B1 (ko) * 1996-12-31 2000-03-15 윤종용 반도체메모리장치의로우리던던시구조및불량셀구제방법
JPH11203890A (ja) * 1998-01-05 1999-07-30 Mitsubishi Electric Corp 半導体記憶装置
US6188618B1 (en) * 1998-04-23 2001-02-13 Kabushiki Kaisha Toshiba Semiconductor device with flexible redundancy system
JP3880210B2 (ja) * 1998-08-04 2007-02-14 エルピーダメモリ株式会社 半導体装置
JP2000182390A (ja) * 1998-12-11 2000-06-30 Mitsubishi Electric Corp 半導体記憶装置
JP2000182370A (ja) * 1998-12-16 2000-06-30 Toshiba Corp 半導体記憶装置
JP3474474B2 (ja) * 1998-12-21 2003-12-08 モトローラ株式会社 半導体メモリ装置
JP2000235800A (ja) * 1999-02-12 2000-08-29 Mitsubishi Electric Corp 半導体記憶装置
JP2000285693A (ja) * 1999-03-31 2000-10-13 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP2000340766A (ja) * 1999-05-31 2000-12-08 Fujitsu Ltd 半導体記憶装置
JP4439683B2 (ja) * 1999-06-03 2010-03-24 三星電子株式会社 リダンダンシ選択回路を備えたフラッシュメモリ装置及びテスト方法
JP2001052496A (ja) * 1999-06-04 2001-02-23 Matsushita Electric Ind Co Ltd 半導体記憶装置
US6219286B1 (en) * 1999-06-04 2001-04-17 Matsushita Electric Industrial Co., Ltd. Semiconductor memory having reduced time for writing defective information
JP4748828B2 (ja) * 1999-06-22 2011-08-17 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP2001101890A (ja) * 1999-09-28 2001-04-13 Mitsubishi Electric Corp 半導体記憶装置
JP3822412B2 (ja) * 2000-03-28 2006-09-20 株式会社東芝 半導体記憶装置
JP2001297595A (ja) * 2000-04-13 2001-10-26 Mitsubishi Electric Corp 半導体記憶装置及び半導体集積回路装置
US6421284B1 (en) * 2000-05-26 2002-07-16 Hitachi, Limited Semiconductor device
JP3967526B2 (ja) * 2000-06-05 2007-08-29 富士通株式会社 半導体記憶装置及び半導体記憶装置の制御方法
JP2002008370A (ja) * 2000-06-21 2002-01-11 Mitsubishi Electric Corp 半導体記憶装置
US6584022B2 (en) * 2000-08-21 2003-06-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with simultaneous data line selection and shift redundancy selection
US6667917B1 (en) * 2001-06-15 2003-12-23 Artisan Components, Inc. System and method for identification of faulty or weak memory cells under simulated extreme operating conditions

Also Published As

Publication number Publication date
US20040062114A1 (en) 2004-04-01
US6999358B2 (en) 2006-02-14
KR20020077026A (ko) 2002-10-11
EP1246200B1 (de) 2007-06-27
JP3945993B2 (ja) 2007-07-18
DE60129104T2 (de) 2007-10-25
EP1246200A2 (de) 2002-10-02
CN100477001C (zh) 2009-04-08
US20020141262A1 (en) 2002-10-03
EP1246200A3 (de) 2004-07-07
KR100757760B1 (ko) 2007-09-12
CN1379410A (zh) 2002-11-13
US6654298B2 (en) 2003-11-25
JP2002298593A (ja) 2002-10-11
TW533429B (en) 2003-05-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE