DE60033467D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE60033467D1
DE60033467D1 DE60033467T DE60033467T DE60033467D1 DE 60033467 D1 DE60033467 D1 DE 60033467D1 DE 60033467 T DE60033467 T DE 60033467T DE 60033467 T DE60033467 T DE 60033467T DE 60033467 D1 DE60033467 D1 DE 60033467D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60033467T
Other languages
English (en)
Other versions
DE60033467T2 (de
Inventor
Masahiko Nagatomo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE60033467D1 publication Critical patent/DE60033467D1/de
Application granted granted Critical
Publication of DE60033467T2 publication Critical patent/DE60033467T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
DE60033467T 1999-05-20 2000-03-10 Halbleiterspeicheranordnung Expired - Lifetime DE60033467T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP13964199 1999-05-20
JP13964199A JP3497770B2 (ja) 1999-05-20 1999-05-20 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE60033467D1 true DE60033467D1 (de) 2007-04-05
DE60033467T2 DE60033467T2 (de) 2007-11-29

Family

ID=15250019

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60033467T Expired - Lifetime DE60033467T2 (de) 1999-05-20 2000-03-10 Halbleiterspeicheranordnung

Country Status (6)

Country Link
US (1) US6243297B1 (de)
EP (1) EP1054408B1 (de)
JP (1) JP3497770B2 (de)
KR (1) KR100605275B1 (de)
DE (1) DE60033467T2 (de)
TW (1) TW525172B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010080651A (ko) * 1999-10-04 2001-08-22 구사마 사부로 반도체 집적회로, 이 반도체 집적회로를 갖는 잉크카트리지, 및, 이 잉크 카트리지를 장착한 잉크젯 기록장치
US6567314B1 (en) * 2000-12-04 2003-05-20 Halo Lsi, Inc. Data programming implementation for high efficiency CHE injection
JP4286085B2 (ja) 2003-07-28 2009-06-24 Ｏｋｉセミコンダクタ株式会社 増幅器及びそれを用いた半導体記憶装置
US7110303B2 (en) * 2004-02-25 2006-09-19 Analog Devices, Inc. Memory cell testing feature
KR20050087719A (ko) * 2004-02-26 2005-08-31 오끼 덴끼 고오교 가부시끼가이샤 반도체 기억장치
JP4615297B2 (ja) * 2004-02-26 2011-01-19 Ｏｋｉセミコンダクタ株式会社 半導体記憶装置
US6944041B1 (en) * 2004-03-26 2005-09-13 Bae Systems Information And Electronic Systems Integration, Inc. Circuit for accessing a chalcogenide memory array
JP2006065968A (ja) 2004-08-27 2006-03-09 Oki Electric Ind Co Ltd 半導体記憶装置のデータ書き込み回路およびデータ書き込み方法
JP5028007B2 (ja) * 2005-12-01 2012-09-19 ラピスセミコンダクタ株式会社 不揮発性記憶装置およびその書込み方法
JP2008047224A (ja) * 2006-08-17 2008-02-28 Oki Electric Ind Co Ltd 不揮発性半導体メモリ
US7916544B2 (en) * 2008-01-25 2011-03-29 Micron Technology, Inc. Random telegraph signal noise reduction scheme for semiconductor memories

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4344154A (en) * 1980-02-04 1982-08-10 Texas Instruments Incorporated Programming sequence for electrically programmable memory
US5229963A (en) * 1988-09-21 1993-07-20 Kabushiki Kaisha Toshiba Semiconductor nonvolatile memory device for controlling the potentials on bit lines
DE69128635T2 (de) * 1990-09-25 1998-05-20 Toshiba Kawasaki Kk Nicht-flüchtiger halbleiterspeicher
EP0757356B1 (de) * 1995-07-31 2001-06-06 STMicroelectronics S.r.l. Flash-EEPROM mit gesteuerter Entladungszeit der Wortleitungs- und Sourcespannungen nach der Löschung
US5657268A (en) * 1995-11-20 1997-08-12 Texas Instruments Incorporated Array-source line, bitline and wordline sequence in flash operations

Also Published As

Publication number Publication date
KR100605275B1 (ko) 2006-07-26
TW525172B (en) 2003-03-21
EP1054408B1 (de) 2007-02-21
JP3497770B2 (ja) 2004-02-16
EP1054408A2 (de) 2000-11-22
DE60033467T2 (de) 2007-11-29
US6243297B1 (en) 2001-06-05
KR20000076844A (ko) 2000-12-26
JP2000331486A (ja) 2000-11-30
EP1054408A3 (de) 2002-07-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP