DE4041897C2 - Integrierte Schaltkreiseinrichtung und Abtastpfadsystem - Google Patents

Integrierte Schaltkreiseinrichtung und Abtastpfadsystem

Info

Publication number
DE4041897C2
DE4041897C2 DE4041897A DE4041897A DE4041897C2 DE 4041897 C2 DE4041897 C2 DE 4041897C2 DE 4041897 A DE4041897 A DE 4041897A DE 4041897 A DE4041897 A DE 4041897A DE 4041897 C2 DE4041897 C2 DE 4041897C2
Authority
DE
Germany
Prior art keywords
data
shift register
selection
integrated circuit
selection data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE4041897A
Other languages
German (de)
English (en)
Other versions
DE4041897A1 (de
Inventor
Takeshi Hashizume
Kazuhiro Sakashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE4041897A1 publication Critical patent/DE4041897A1/de
Application granted granted Critical
Publication of DE4041897C2 publication Critical patent/DE4041897C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
DE4041897A 1989-12-27 1990-12-27 Integrierte Schaltkreiseinrichtung und Abtastpfadsystem Expired - Fee Related DE4041897C2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP34106489 1989-12-27
JP2314545A JP2676169B2 (ja) 1989-12-27 1990-11-19 スキャンパス回路

Publications (2)

Publication Number Publication Date
DE4041897A1 DE4041897A1 (de) 1991-07-11
DE4041897C2 true DE4041897C2 (de) 1996-10-24

Family

ID=26567981

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4041897A Expired - Fee Related DE4041897C2 (de) 1989-12-27 1990-12-27 Integrierte Schaltkreiseinrichtung und Abtastpfadsystem

Country Status (3)

Country Link
US (1) US5260949A (ja)
JP (1) JP2676169B2 (ja)
DE (1) DE4041897C2 (ja)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0455778A (ja) * 1990-06-26 1992-02-24 Toshiba Corp 半導体装置のテスト方法
JP2742740B2 (ja) * 1991-03-20 1998-04-22 三菱電機株式会社 バイパススキャンパスおよびそれを用いた集積回路装置
US5221865A (en) * 1991-06-21 1993-06-22 Crosspoint Solutions, Inc. Programmable input/output buffer circuit with test capability
JP2741119B2 (ja) * 1991-09-17 1998-04-15 三菱電機株式会社 バイパススキャンパスおよびそれを用いた集積回路装置
GB9217728D0 (en) * 1992-08-20 1992-09-30 Texas Instruments Ltd Method of testing interconnections between integrated circuits in a circuit
US5627838A (en) * 1993-09-30 1997-05-06 Macronix International Co., Ltd. Automatic test circuitry with non-volatile status write
US5418470A (en) * 1993-10-22 1995-05-23 Tektronix, Inc. Analog multi-channel probe system
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
US5535222A (en) * 1993-12-23 1996-07-09 At&T Corp. Method and apparatus for controlling a plurality of systems via a boundary-scan port during testing
US5815512A (en) * 1994-05-26 1998-09-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory testing device
GB2290877B (en) * 1994-07-01 1997-08-20 Advanced Risc Mach Ltd Integrated circuit test controller
US5572599A (en) * 1994-07-11 1996-11-05 Xerox Corporation Monochrome to full color scaleable image processing system for printing systems and machines
US5623502A (en) * 1994-07-15 1997-04-22 National Semiconductor Corporation Testing of electronic circuits which typically contain asynchronous digital circuitry
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US5479127A (en) * 1994-11-10 1995-12-26 National Semiconductor Corporation Self-resetting bypass control for scan test
US5732091A (en) * 1994-11-21 1998-03-24 Texas Instruments Incorporated Self initializing and correcting shared resource boundary scan with output latching
US5715254A (en) * 1994-11-21 1998-02-03 Texas Instruments Incorporated Very low overhead shared resource boundary scan design
SE504041C2 (sv) * 1995-03-16 1996-10-21 Ericsson Telefon Ab L M Integrerat kretsarrangemang för provning
US6055659A (en) * 1999-02-26 2000-04-25 Texas Instruments Incorporated Boundary scan with latching output buffer and weak input buffer
DE19536226C2 (de) * 1995-09-28 2003-05-08 Infineon Technologies Ag Testbare Schaltungsanordnung mit mehreren identischen Schaltungsblöcken
US6005407A (en) * 1995-10-23 1999-12-21 Opmax Inc. Oscillation-based test method for testing an at least partially analog circuit
US5719878A (en) * 1995-12-04 1998-02-17 Motorola Inc. Scannable storage cell and method of operation
JP3691144B2 (ja) * 1995-12-20 2005-08-31 株式会社ルネサステクノロジ スキャンパス構成回路
US5719879A (en) * 1995-12-21 1998-02-17 International Business Machines Corporation Scan-bypass architecture without additional external latches
US5710779A (en) * 1996-04-09 1998-01-20 Texas Instruments Incorporated Real time data observation method and apparatus
JP3614993B2 (ja) * 1996-09-03 2005-01-26 株式会社ルネサステクノロジ テスト回路
US5812561A (en) * 1996-09-03 1998-09-22 Motorola, Inc. Scan based testing of an integrated circuit for compliance with timing specifications
US5774476A (en) * 1997-02-03 1998-06-30 Motorola, Inc. Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit
US5889788A (en) * 1997-02-03 1999-03-30 Motorola, Inc. Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation
US6031385A (en) * 1997-03-24 2000-02-29 Intel Corporation Method and apparatus for testing compensated buffer circuits
US6362015B1 (en) * 1998-10-30 2002-03-26 Texas Instruments Incorporated Process of making an integrated circuit using parallel scan paths
JPH11142482A (ja) * 1997-11-13 1999-05-28 Fujitsu Ltd タイミング故障診断方法及び装置
US6405335B1 (en) * 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6178534B1 (en) * 1998-05-11 2001-01-23 International Business Machines Corporation System and method for using LBIST to find critical paths in functional logic
JP2000214220A (ja) * 1999-01-19 2000-08-04 Texas Instr Inc <Ti> オンチップモジュ―ルおよびオンチップモジュ―ル間の相互接続をテストするシステムおよび方法
JP2000258506A (ja) * 1999-03-12 2000-09-22 Mitsubishi Electric Corp 半導体集積回路およびそのテストパターン生成方法
JP2000275303A (ja) * 1999-03-23 2000-10-06 Mitsubishi Electric Corp バウンダリスキャンテスト方法及びバウンダリスキャンテスト装置
WO2000073809A1 (fr) * 1999-05-26 2000-12-07 Hitachi, Ltd. Circuit integre a semi-conducteur
US7171347B2 (en) * 1999-07-02 2007-01-30 Intel Corporation Logic verification in large systems
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
DE10132159B4 (de) * 2001-07-03 2004-03-11 Infineon Technologies Ag Verfahren und Vorrichtung zum gleichzeitigen Testen einer Mehrzahl von integrierten Schaltungen
US6836865B2 (en) * 2001-10-09 2004-12-28 International Business Machines Corporation Method and apparatus for facilitating random pattern testing of logic structures
US6894501B1 (en) * 2002-05-21 2005-05-17 Volterra Semiconductor, Inc. Selecting multiple settings for an integrated circuit function using a single integrated circuit terminal
JP2008520980A (ja) * 2004-11-22 2008-06-19 フリースケール セミコンダクター インコーポレイテッド 集積回路及びマルチｔａｐ集積回路を試験する方法
JP2007294015A (ja) * 2006-04-25 2007-11-08 Matsushita Electric Ind Co Ltd 半導体集積回路、及びｂｉｓｔ回路設計方法
WO2008041292A1 (fr) * 2006-09-29 2008-04-10 Fujitsu Limited Circuit intégré
JP5035665B2 (ja) * 2007-03-19 2012-09-26 日本電気株式会社 半導体集積回路、半導体集積回路のテストパターン生成装置
JP4802139B2 (ja) * 2007-05-15 2011-10-26 株式会社東芝 半導体集積回路モジュール
US7954022B2 (en) * 2008-01-30 2011-05-31 Alcatel-Lucent Usa Inc. Apparatus and method for controlling dynamic modification of a scan path
US8095837B2 (en) * 2008-03-19 2012-01-10 International Business Machines Corporation Method and apparatus for improving random pattern testing of logic structures
JP5625249B2 (ja) * 2009-03-24 2014-11-19 富士通株式会社 回路モジュール、半導体集積回路、および検査装置
JP5338840B2 (ja) * 2011-04-01 2013-11-13 日本テキサス・インスツルメンツ株式会社 半導体集積回路
US9891864B2 (en) 2016-01-19 2018-02-13 Micron Technology, Inc. Non-volatile memory module architecture to support memory error correction

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698588A (en) * 1985-10-23 1987-10-06 Texas Instruments Incorporated Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit
US4701921A (en) * 1985-10-23 1987-10-20 Texas Instruments Incorporated Modularized scan path for serially tested logic circuit
JPS62220879A (ja) * 1986-03-22 1987-09-29 Hitachi Ltd 半導体装置
JPS63182585A (ja) * 1987-01-26 1988-07-27 Toshiba Corp テスト容易化機能を備えた論理回路
US4872169A (en) * 1987-03-06 1989-10-03 Texas Instruments Incorporated Hierarchical scan selection
JPS63256877A (ja) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp テスト回路
GB2210171B (en) * 1987-09-28 1991-06-26 Plessey Co Plc Test circuit
JPH01270683A (ja) * 1988-04-22 1989-10-27 Mitsubishi Electric Corp 半導体集積回路
US5084874A (en) * 1988-09-07 1992-01-28 Texas Instruments Incorporated Enhanced test circuit
US5056093A (en) * 1989-08-09 1991-10-08 Texas Instruments Incorporated System scan path architecture
US5054024A (en) * 1989-08-09 1991-10-01 Texas Instruments Incorporated System scan path architecture with remote bus controller
JP2626920B2 (ja) * 1990-01-23 1997-07-02 三菱電機株式会社 スキャンテスト回路およびそれを用いた半導体集積回路装置
JP2627464B2 (ja) * 1990-03-29 1997-07-09 三菱電機株式会社 集積回路装置
JP2908919B2 (ja) * 1991-10-04 1999-06-23 高砂香料工業株式会社 光学活性有機ケイ素化合物の製造方法
JP3304490B2 (ja) * 1993-04-08 2002-07-22 住友化学工業株式会社 ヘキサメチルテトラリンの精製法

Also Published As

Publication number Publication date
JPH03233375A (ja) 1991-10-17
DE4041897A1 (de) 1991-07-11
US5260949A (en) 1993-11-09
JP2676169B2 (ja) 1997-11-12

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: PRUFER & PARTNER GBR, 81545 MUENCHEN

8339 Ceased/non-payment of the annual fee