DE4010610A1 - Dram-zellen anordnung unter verwendung geschichteter, kombinierter kondensatoren und verfahren zu deren herstellung - Google Patents

Dram-zellen anordnung unter verwendung geschichteter, kombinierter kondensatoren und verfahren zu deren herstellung

Info

Publication number
DE4010610A1
DE4010610A1 DE4010610A DE4010610A DE4010610A1 DE 4010610 A1 DE4010610 A1 DE 4010610A1 DE 4010610 A DE4010610 A DE 4010610A DE 4010610 A DE4010610 A DE 4010610A DE 4010610 A1 DE4010610 A1 DE 4010610A1
Authority
DE
Germany
Prior art keywords
capacitor
layer
channel
layered
silicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE4010610A
Other languages
German (de)
English (en)
Inventor
Dong Won Kim
Young Jong Lee
Young Gon Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Goldstar Electron Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Goldstar Electron Co Ltd filed Critical Goldstar Electron Co Ltd
Publication of DE4010610A1 publication Critical patent/DE4010610A1/de
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/038Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/377DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
DE4010610A 1989-08-31 1990-04-02 Dram-zellen anordnung unter verwendung geschichteter, kombinierter kondensatoren und verfahren zu deren herstellung Ceased DE4010610A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890012491A KR950000500B1 (ko) 1989-08-31 1989-08-31 디램셀 커패시터 제조방법 및 구조

Publications (1)

Publication Number Publication Date
DE4010610A1 true DE4010610A1 (de) 1991-03-14

Family

ID=19289455

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4010610A Ceased DE4010610A1 (de) 1989-08-31 1990-04-02 Dram-zellen anordnung unter verwendung geschichteter, kombinierter kondensatoren und verfahren zu deren herstellung

Country Status (6)

Country Link
JP (1) JPH03116970A (ko)
KR (1) KR950000500B1 (ko)
DE (1) DE4010610A1 (ko)
FR (1) FR2651374A1 (ko)
GB (1) GB2235578A (ko)
NL (1) NL9000800A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4103596A1 (de) * 1990-10-11 1992-04-16 Samsung Electronics Co Ltd Misi-dram-zelle und verfahren zu ihrer herstellung

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930007194B1 (ko) * 1990-08-14 1993-07-31 삼성전자 주식회사 반도체 장치 및 그 제조방법
KR960026870A (ko) * 1994-12-31 1996-07-22 김주용 반도체소자의 캐패시터 제조방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0223616A2 (en) * 1985-11-20 1987-05-27 Kabushiki Kaisha Toshiba Semiconductor memory device and manufacturing method
DE3916228A1 (de) * 1988-05-18 1989-11-30 Toshiba Kawasaki Kk Halbleiterspeichervorrichtung mit stapelkondensatorzellenstruktur und verfahren zu ihrer herstellung

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685427B2 (ja) * 1986-03-13 1994-10-26 三菱電機株式会社 半導体記憶装置
JPS63146461A (ja) * 1986-12-10 1988-06-18 Mitsubishi Electric Corp 半導体記憶装置
JPS63239969A (ja) * 1987-03-27 1988-10-05 Sony Corp メモリ装置
JPH01101664A (ja) * 1987-10-15 1989-04-19 Nec Corp 半導体集積回路装置
JPH0666437B2 (ja) * 1987-11-17 1994-08-24 富士通株式会社 半導体記憶装置及びその製造方法
JPH01192163A (ja) * 1988-01-28 1989-08-02 Toshiba Corp 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0223616A2 (en) * 1985-11-20 1987-05-27 Kabushiki Kaisha Toshiba Semiconductor memory device and manufacturing method
DE3916228A1 (de) * 1988-05-18 1989-11-30 Toshiba Kawasaki Kk Halbleiterspeichervorrichtung mit stapelkondensatorzellenstruktur und verfahren zu ihrer herstellung

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4103596A1 (de) * 1990-10-11 1992-04-16 Samsung Electronics Co Ltd Misi-dram-zelle und verfahren zu ihrer herstellung

Also Published As

Publication number Publication date
FR2651374A1 (fr) 1991-03-01
KR950000500B1 (ko) 1995-01-24
JPH03116970A (ja) 1991-05-17
NL9000800A (nl) 1991-03-18
GB9007157D0 (en) 1990-05-30
KR910005305A (ko) 1991-03-30
GB2235578A (en) 1991-03-06

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection