GB2235578A - Capacitors for dram cells - Google Patents

Capacitors for dram cells Download PDF

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Publication number
GB2235578A
GB2235578A GB9007157A GB9007157A GB2235578A GB 2235578 A GB2235578 A GB 2235578A GB 9007157 A GB9007157 A GB 9007157A GB 9007157 A GB9007157 A GB 9007157A GB 2235578 A GB2235578 A GB 2235578A
Authority
GB
United Kingdom
Prior art keywords
layer
trenches
stacked capacitors
contact windows
dram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9007157A
Other versions
GB9007157D0 (en
Inventor
Dong Won Kim
Young Jong Lee
Young Gon Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Goldstar Electron Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Goldstar Electron Co Ltd filed Critical Goldstar Electron Co Ltd
Publication of GB9007157D0 publication Critical patent/GB9007157D0/en
Publication of GB2235578A publication Critical patent/GB2235578A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor

Abstract

Each DRAM cell includes a stack capacitor 14 and a trench capacitor 15 so that in an assembly of such cells similar capacitors are arranged on diagonal lines and each capacitor of one type is surrounded on four sides by capacitors of the other type. The arrangement enables a smoother device topology and also prevents leakage current between trenches. <IMAGE>

Description

DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME The present invention relates to a DRAM (Dynamic Random Access Memory), and to a method of manufacturing a DRAM.
Efforts are being made to increase the integration of DRAMs. A limiting factor is the need to provide a capacitor in each memory cell with sufficient capacitance to retain reliably charges associated with stored data. Recently, so as to reduce the area occupied by the memory cell capacitors, stacked capacitors have been proposed having a verticallystacked structure. Two types of proposed stacked capacitor are a so-called higher stacked capacitor (high stacked capacitor) and a trench stacked capacitor. However, in each case, DRAM cells incorporating these types of capacitor suffer from problems as will be explained later.
According to a first aspect of the present invention, there is provided a DRAM in which higher stacked capacitors and trench stacked capacitors are alternately arranged over a substrate to provide the memory cell capacitors.
Preferably, contact windows for the higher stacked capacitors and trenches for the trench stacked capacitors are each respectively arranged in a diagonal formation. This means that each higher stacked capacitor is bordered on four sides by trench stacked capacitors, and vice-versa.
According to a second aspect of the present invention, there is provided a method of manufacturing a DRAM, comprising steps of providing a substrate with an array of transistors, forming trenches in the substrate, forming a thick silicon layer over the whole substrate, opening contact windows in areas of the thick silicon layer located between adjacent trenches, etching the remaining thick silicon layer except around the contact windows, forming a storage node layer in the contact windows and in the trenches, and forming a dielectric film on the storage node layer; whereby alternately arranged trench stacked capacitors and higher stacked capacitors are formed in and around the trenches and contact windows respectively.
Preferably, the depth of the trenches and the thickness of the thick silicon layer are adjusted so as to obtain an equivalent capacitance of the trench stacked capacitors and the higher stacked capacitors, after taking into account the substrate area allowed for each capacitor under the design rule being followed, and the extra vertical area obtained in each case.
Thus, the present invention can provide a DRAM which incorporates two different types of memory cell capacitor. That is, the cell construction employs a stacked combination capacitor which is constructed by alternately combining a higher stacked capacitor and a trench stacked capacitor. This can reduce or avoid altogether the problems of narrow spaces and design rule contravention of storage nodes occurring with higher stacked capacitors, and also solve the problem of the closest trench-to-trench isolation arising with trench stacked capacitors.
Reference will now be made, by way of example, to the accompanying drawings in which: Fig. 1 is a plan view of a previously proposed DRAM cell employing a higher stacked capacitor; Fig. 2 is a sectional view along the line B-B' in Fig. 1; Fig. 3 is a plan view of another previously proposed DRAM cell employing a trench stacked capacitor; Fig. 4 is a sectional view along the line B-B' in Fig. 3; Fig. 5 is a plan view of a DRAM cell embodying the present invention, employing a stacked combination capacitor; Figs. 6(A) to (F) show processes for manufacturing a DRAM embodying the present invention, illustrated by sectional views along the line A-A' in Fig. 5; and Fig. 7 is a sectional view along the line B-B' in Fig. 5.
The reference numerals in the drawings designate the following: 1 is a contact window of a higher stacked capacitor, 2 is a contact window (trench) of a trench stacked capacitor, 3 is a capacitor area, 4 a word line, 5 a contact window of an interconnection line (bit line), 6 a field oxide layer, 7 a CVD oxide layer, 8 a dopant diffusion area, 9 a photoresist, 10 a thick silicon layer, lOa a region of the thick defined silicon layer remaining after etching, 11 a silicon layer for forming storage nodes, 12 a thin dielectric film, 13 a silicon layer, 14 a higher stacked capacitor and 15 a trench stacked capacitor.
In prior proposals, as shown in Figs. 1 to 4, an increase of the capacitance of a stacked capacitor has been accomplished either by stacking a thick polycrystalline silicon layer to increase the height of the capacitor (to form a so-called higher stacked capacitor), or by forming the capacitor in a shallow trench (to form a so-called trench stacked capacitor).
Manufacturing processes for each of these two types of structure will now be described.
Figures 1 and 2 illustrate the employment of a higher stacked capacitor in a DRAM cell. To produce this structure, a CVD (chemical vapor deposition) oxide layer 7 and thick poly silicon layer lOa are sequentially deposited on already-defined gates (transistors). Higher stacked capacitor contact windows 1 are then opened by RIE (reactive ion etching). A silicon layer 11 for a storage node is then deposited by CVD, and doped using either ion implantation or diffusion of POC13 vapor.
Subsequently, the capacitor area 3, stacked with thick silicon layer 10a and storage node silicon layer 11, is defined (etched) by conventional photolithography and etching processes. Finally, a thin dielectric film 12 is formed on the storage node silicon layer 11 and a polysilicon layer 13 for plate is deposited.
Referring to Figs. 3 and 4, the manufacturing processes of a DRAM cell incorporating a trench stacked capacitor are as follows. A CVD oxide layer 7 is deposited by CVD on previously defined gates; contact windows are opened by reactive ion etching (RIE) between the gates and the oxide is etched down to the silicon substrate. Trenches 2 are then formed by etching into the silicon substrate and are lined with a storage silicon layer 11 doped using ion implantation or POC13 vapor diffusion. Finally the capacitor area is defined, and the thin dielectric film 12 and plate silicon layer 13 are deposited sequentially.
With the DRAM cell construction employing a higher stacked capacitor, the increment in the vertical area by: a large silicon thickness x (the thickness of the capacitor periphery + the thickness of the contact window periphery) increases the capacitance of the DRAM cell considerably relative to a stacked capacitor without a thick silicon layer.
In the DRAM cell construction employing a trench stacked capacitor, the doping into the silicon layer 11 for storage nodes results in automatic diffusion of the dopant in the surroundings of the trench, and the capacitance increases by the amount of (trench depth x contact window peripheral area) compared to a conventional stacked capacitor.
However, there are drawbacks with the two types of construction described above.
In the higher stacked capacitor DRAM cell, the defined storage node silicon layer 11 has to cover the whole contact window 1 in spite of the misalignment in the direction of the line B-B' in Fig. 1. Therefore, it can prove difficult in practice to employ the design as shown in Fig. 1. As shown in Fig. 2, the space between two storage nodes 11 on field oxide 6 is so narrow that a concave region with a large aspect ratio Ra(Ra > 1.2) may be formed. This places a practical limitation on the thickness of the silicon layer lOa.
In the trench stacked capacitor DRAM cell as shown in Fig. 3 and Fig. 4, the poly silicon 11 comes in contact with almost the entire dopant diffused region 8 formed around the trench 2 so as to minimise any problem of contact resistance. However, electrical interaction between the neighboring dopant diffused regions of the trenches causes a leakage current, which is likely to become more serious as the distance between trenches is narrowed for higher and higher integration.
A DRAM cell construction embodying the present invention, employing a stacked combination capacitor, and method for manufacturing the same, will now be described in detail with reference to Figures 5 to 7.
Fig. 5 shows a basic construction of a DRAM cell which employs in combination both the higher stacked capacitor and the trench stacked capacitor, so as to compensate for the problems resulting from applying each type of construction to a DRAM cell independently.
In this construction, trenches 2 of the trench stacked capacitors are placed in a diagonal arrangement relative to the contact windows 1 of the higher stacked capacitors, with each capacitor area 3 covering the contact window 1 and trench 2 respectively, and with a word line 4 formed just beside the window 1 and the trench 2 between which the bit line contact window 5 is placed.
Figs. 6(A) to (F) illustrate a sequence of manufacturing steps for this construction. As shown in Fig. 6(A), a CVD oxide-layer 7 is deposited on the surface of a substrate having gates 4 previously formed by the same steps as for fabricating a conventional DRAM. In Fig. 6(B), trenches 2 are formed by etching down to the substrate, the other regions being protected by a photoresist 9. In Fig. 6(C), poly or amorphous silicon is deposited up to a depth of 3000 A (300 nm) or more by CVD for forming a thick silicon layer 10, whose thickness should be adjusted so that the capacitance of each higher stacked capacitor is equivalent to that of each trench stacked capacitor in the finished device.Thereafter, a contact window 1 is opened to contact with the remaining diffused regions which are later to form higher stacked capacitors, all the regions except the window 1 being protected by a photoresist layer.
In Fig. 6(D), after defining a thick silicon layer 10a (by etching the thick silicon layer 10), the silicon on the trench region is completely stripped off. In Fig. 6(E), a silicon layer 11 for forming storage nodes is deposited, doped and defined on both capacitors in the window 1 and the trench 2; and in Fig. 6(F), a thin dielectric layer for the capacitor is formed and the polysilicon layer 13 is deposited. The finished structure shown in Fig. 6(F)- and Fig. 7 has side-by-side higher stacked capacitors (14) and trench stacked capacitors (15).
Thus, a DRAM embodying the present invention includes alternately-formed higher stacked capacitors and trench stacked capacitors to provide the DRAM cell capacitors, the thickness of a thick silicon layer in each higher stacked capacitor, and the depth of the trench in each trench stacked capacitor, being adjusted to harmonize the capacitance. Furthermore, as shown in Fig. 7, since the higher stacked capacitor and the shallow trench capacitor both employ thick silicon layers and are formed alternately, the space between the higher stacked layers is enlarged so as to not only smooth the topology of the top layer but also satisfy the design rule. Moreover, the minimum distance between the diffusion areas surrounding the trenches can be increased by around 2.5 times, bringing the further advantage of minimising leakage currents between trenches.

Claims (12)

1. A DRAM in which higher stacked capacitors and trench stacked capacitors are alternately arranged over a substrate to provide the memory cell capacitors.
2. A DRAM as claimed in claim 1, wherein contact windows for the higher stacked capacitors and trenches for the trench stacked capacitors are each respectively arranged in a diagonal formation.
3. A DRAM as claimed in claim 1 or 2, having trenches formed in the substrate for the trench stacked capacitors and contact windows formed for the higher stacked capacitors, thick silicon regions around the contact windows, a storage node layer in the trenches and contact windows, and a dielectric film covering the storage node layer.
4. A DRAM as claimed in claim 3, further comprising an overall plate layer as a top layer, having a topology which is relatively smooth in comparison with DRAMs having exclusively higher stacked capacitors.
5. A method of manufacturing a DRAM, comprising steps of: providing a substrate with an array of transistors, forming trenches in the substrate, forming a thick silicon layer over the whole substrate, opening contact windows in areas of the thick silicon layer located between adjacent trenches, etching the remaining thick silicon layer except around the contact windows, forming a storage node layer in the contact windows and in the trenches, and forming a dielectric film on the storage node layer; whereby alternately arranged trench stacked capacitors and higher stacked capacitors are formed in and around the trenches and contact windows respectively.
6. A method as claimed in claim 5, comprising a further step of depositing an overall plate layer having a relatively smooth topology.
7. A method as claimed in claim 6, wherein the substrate is provided with a CVD oxide coating for isolation on the transistors, prior to the step of forming the trenches, wherein the storage node layer is formed of silicon, and wherein the plate layer is formed of polycrystalline silicon.
8. A method as claimed in claim 7, wherein in the step of opening the contact windows for the higher stacked capacitors, areas of the thick silicon layer and CVD oxide layer are completely removed to expose dopant diffused regions of the substrate.
9. A method as claimed in claim 5, 6, 7 or 8, wherein the depth of the trenches and the thickness of the thick silicon layer are adjusted, the thickness of deposition of the latter reaching up to hundreds nm, so as to obtain an equivalent capacitance of the trench stacked capacitors and the higher stacked capacitors after taking into account the increment of area for the design rule and the vertical area.
10. A method as claimed in any of claims 5 to 9, wherein in the step of etching the thick silicon layer, said layer is completely removed except in the areas for the higher stacked capacitors around the contact windows.
11. A DRAM substantially as hereinbefore described with reference to Figures 5 to 7 of the accompanying drawings.
12. A method of manufacturing a DRAM substantially as hereinbefore described with reference to Figures 5 to 7 of the accompanying drawings.
GB9007157A 1989-08-31 1990-03-30 Capacitors for dram cells Withdrawn GB2235578A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890012491A KR950000500B1 (en) 1989-08-31 1989-08-31 Manufacturing method and structure of dram cell capacitor

Publications (2)

Publication Number Publication Date
GB9007157D0 GB9007157D0 (en) 1990-05-30
GB2235578A true GB2235578A (en) 1991-03-06

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GB9007157A Withdrawn GB2235578A (en) 1989-08-31 1990-03-30 Capacitors for dram cells

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JP (1) JPH03116970A (en)
KR (1) KR950000500B1 (en)
DE (1) DE4010610A1 (en)
FR (1) FR2651374A1 (en)
GB (1) GB2235578A (en)
NL (1) NL9000800A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2247105B (en) * 1990-08-14 1995-04-05 Samsung Electronics Co Ltd Highly integrated semiconductor memory device and method of manufacture therefor
GB2296821A (en) * 1994-12-31 1996-07-10 Hyundai Electronics Ind Method for fabricating capacitors of semiconductor devices

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930005738B1 (en) * 1990-10-11 1993-06-24 삼성전자 주식회사 Mist type dynamic random access memory cell and method for fabricating thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0237361A2 (en) * 1986-03-13 1987-09-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62120070A (en) * 1985-11-20 1987-06-01 Toshiba Corp Semiconductor memory
JPS63146461A (en) * 1986-12-10 1988-06-18 Mitsubishi Electric Corp Semiconductor memory device
JPS63239969A (en) * 1987-03-27 1988-10-05 Sony Corp Memory device
JPH01101664A (en) * 1987-10-15 1989-04-19 Nec Corp Semiconductor integrated circuit device
JPH0666437B2 (en) * 1987-11-17 1994-08-24 富士通株式会社 Semiconductor memory device and manufacturing method thereof
JPH01192163A (en) * 1988-01-28 1989-08-02 Toshiba Corp Manufacture of semiconductor device
DE3916228C2 (en) * 1988-05-18 1995-06-22 Toshiba Kawasaki Kk Semiconductor memory device with stacked capacitor cell structure and method for its production

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0237361A2 (en) * 1986-03-13 1987-09-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2247105B (en) * 1990-08-14 1995-04-05 Samsung Electronics Co Ltd Highly integrated semiconductor memory device and method of manufacture therefor
GB2296821A (en) * 1994-12-31 1996-07-10 Hyundai Electronics Ind Method for fabricating capacitors of semiconductor devices
GB2296821B (en) * 1994-12-31 1999-01-20 Hyundai Electronics Ind Method for fabricating capacitors of semiconductor device

Also Published As

Publication number Publication date
JPH03116970A (en) 1991-05-17
KR910005305A (en) 1991-03-30
GB9007157D0 (en) 1990-05-30
DE4010610A1 (en) 1991-03-14
KR950000500B1 (en) 1995-01-24
NL9000800A (en) 1991-03-18
FR2651374A1 (en) 1991-03-01

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WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)