DE4003673A1 - Erweiterte schnellschreibschaltung fuer den dram-test - Google Patents

Erweiterte schnellschreibschaltung fuer den dram-test

Info

Publication number
DE4003673A1
DE4003673A1 DE4003673A DE4003673A DE4003673A1 DE 4003673 A1 DE4003673 A1 DE 4003673A1 DE 4003673 A DE4003673 A DE 4003673A DE 4003673 A DE4003673 A DE 4003673A DE 4003673 A1 DE4003673 A1 DE 4003673A1
Authority
DE
Germany
Prior art keywords
mos transistors
nodes
pair
write
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE4003673A
Other languages
German (de)
English (en)
Other versions
DE4003673C2 (enExample
Inventor
Hoon Choi
Soo-In Cho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE4003673A1 publication Critical patent/DE4003673A1/de
Application granted granted Critical
Publication of DE4003673C2 publication Critical patent/DE4003673C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE4003673A 1989-06-10 1990-02-07 Erweiterte schnellschreibschaltung fuer den dram-test Granted DE4003673A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890008004A KR920001081B1 (ko) 1989-06-10 1989-06-10 램 테스트시 고속기록회로

Publications (2)

Publication Number Publication Date
DE4003673A1 true DE4003673A1 (de) 1990-12-20
DE4003673C2 DE4003673C2 (enExample) 1992-08-27

Family

ID=19286974

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4003673A Granted DE4003673A1 (de) 1989-06-10 1990-02-07 Erweiterte schnellschreibschaltung fuer den dram-test

Country Status (9)

Country Link
US (1) US5140553A (enExample)
JP (1) JP3006768B2 (enExample)
KR (1) KR920001081B1 (enExample)
CN (1) CN1015031B (enExample)
DE (1) DE4003673A1 (enExample)
FR (1) FR2648267B1 (enExample)
GB (1) GB2232774B (enExample)
IT (1) IT1248748B (enExample)
NL (1) NL9000270A (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60195455A (ja) * 1984-03-19 1985-10-03 Toray Ind Inc 血液処理剤
KR920009059B1 (ko) * 1989-12-29 1992-10-13 삼성전자 주식회사 반도체 메모리 장치의 병렬 테스트 방법
JP2838425B2 (ja) * 1990-01-08 1998-12-16 三菱電機株式会社 半導体記憶装置
JP2704041B2 (ja) * 1990-11-09 1998-01-26 日本電気アイシーマイコンシステム株式会社 半導体メモリ装置
JPH04216392A (ja) * 1990-12-18 1992-08-06 Mitsubishi Electric Corp ブロックライト機能を備える半導体記憶装置
US5305263A (en) * 1991-06-12 1994-04-19 Micron Technology, Inc. Simplified low power flash write operation
JPH05128899A (ja) * 1991-10-29 1993-05-25 Mitsubishi Electric Corp 半導体記憶装置
JPH05314763A (ja) * 1992-05-12 1993-11-26 Mitsubishi Electric Corp 半導体記憶装置
JPH0628861A (ja) * 1992-07-07 1994-02-04 Oki Electric Ind Co Ltd 半導体記憶装置
US5241500A (en) * 1992-07-29 1993-08-31 International Business Machines Corporation Method for setting test voltages in a flash write mode
US5392241A (en) * 1993-12-10 1995-02-21 International Business Machines Corporation Semiconductor memory circuit with block overwrite
KR970003270A (ko) * 1995-06-23 1997-01-28 김광호 반도체메모리소자의 테스트를 위한 고속 기록회로
US5568425A (en) * 1996-02-02 1996-10-22 Integrated Silicon Solution, Inc. Program drain voltage control for EPROM/flash
JPH10199296A (ja) * 1997-01-09 1998-07-31 Mitsubishi Electric Corp ダイナミック型半導体記憶装置およびそのテスト方法
US5754486A (en) * 1997-02-28 1998-05-19 Micron Technology, Inc. Self-test circuit for memory integrated circuits
US6125058A (en) * 1999-10-19 2000-09-26 Advanced Micro Devices, Inc. System for optimizing the equalization pulse of a read sense amplifier for a simultaneous operation flash memory device
JP4421615B2 (ja) 2004-12-24 2010-02-24 スパンション エルエルシー 記憶装置のバイアス印加方法、および記憶装置
CN101262380B (zh) * 2008-04-17 2011-04-06 中兴通讯股份有限公司 一种用于fpga仿真的装置及方法
KR102167831B1 (ko) * 2018-06-21 2020-10-21 윈본드 일렉트로닉스 코포레이션 메모리 디바이스 및 그의 테스트 읽기 쓰기 방법
US10566034B1 (en) * 2018-07-26 2020-02-18 Winbond Electronics Corp. Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels
CN115602208B (zh) 2021-07-08 2026-03-27 长鑫存储技术有限公司 一种存储器及其写入方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0282976A1 (de) * 1987-03-16 1988-09-21 Siemens Aktiengesellschaft Verfahren und Schaltungsanordnung zum parallelen Einschreiben von Daten in einen Halbleiterspeicher

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5785255A (en) * 1980-11-17 1982-05-27 Nec Corp Memory storage for integrated circuit
US4567578A (en) * 1982-09-08 1986-01-28 Harris Corporation Cache memory flush scheme
US4587629A (en) * 1983-12-30 1986-05-06 International Business Machines Corporation Random address memory with fast clear
JPS60253093A (ja) * 1984-05-30 1985-12-13 Fujitsu Ltd 半導体記憶装置
JPS61120392A (ja) * 1984-11-15 1986-06-07 Fujitsu Ltd 記憶回路
JP2569010B2 (ja) * 1986-05-21 1997-01-08 株式会社日立製作所 半導体メモリ
JPS6334796A (ja) * 1986-07-28 1988-02-15 Oki Electric Ind Co Ltd 半導体記憶装置
DE3751002T2 (de) * 1986-10-20 1995-10-05 Nippon Telegraph & Telephone Halbleiterspeicher.
JP2523586B2 (ja) * 1987-02-27 1996-08-14 株式会社日立製作所 半導体記憶装置
JPS63244400A (ja) * 1987-03-16 1988-10-11 シーメンス・アクチエンゲゼルシヤフト メモリセルの検査回路装置および方法
JPS63308792A (ja) * 1987-06-10 1988-12-16 Mitsubishi Electric Corp 半導体記憶装置
JPH01106400A (ja) * 1987-10-19 1989-04-24 Hitachi Ltd 半導体記憶装置
JP2579792B2 (ja) * 1987-08-21 1997-02-12 日本電信電話株式会社 冗長構成半導体メモリ
JPH01134799A (ja) * 1987-11-20 1989-05-26 Sony Corp メモリ装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0282976A1 (de) * 1987-03-16 1988-09-21 Siemens Aktiengesellschaft Verfahren und Schaltungsanordnung zum parallelen Einschreiben von Daten in einen Halbleiterspeicher

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Arimoto Kazutami und andere, A 60 ns 3,3V 16Mb DRAM, in: Digest of technical papers, 1989, IEEE International Solid-State Circuits Conference, S. 244 und 245 *

Also Published As

Publication number Publication date
GB2232774B (en) 1994-01-12
GB9002706D0 (en) 1990-04-04
KR920001081B1 (ko) 1992-02-01
KR910001780A (ko) 1991-01-31
IT1248748B (it) 1995-01-27
IT9020564A0 (it) 1990-06-07
FR2648267A1 (fr) 1990-12-14
FR2648267B1 (fr) 1994-03-04
IT9020564A1 (it) 1991-12-07
CN1049742A (zh) 1991-03-06
US5140553A (en) 1992-08-18
CN1015031B (zh) 1991-12-04
DE4003673C2 (enExample) 1992-08-27
JP3006768B2 (ja) 2000-02-07
NL9000270A (nl) 1991-01-02
GB2232774A (en) 1990-12-19
JPH0312900A (ja) 1991-01-21

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition