DE3877525D1 - Halbleiterspeicheranordnung mit einer ladungssperrschicht und verfahren zu ihrer herstellung. - Google Patents

Halbleiterspeicheranordnung mit einer ladungssperrschicht und verfahren zu ihrer herstellung.

Info

Publication number
DE3877525D1
DE3877525D1 DE8888310760T DE3877525T DE3877525D1 DE 3877525 D1 DE3877525 D1 DE 3877525D1 DE 8888310760 T DE8888310760 T DE 8888310760T DE 3877525 T DE3877525 T DE 3877525T DE 3877525 D1 DE3877525 D1 DE 3877525D1
Authority
DE
Germany
Prior art keywords
production
semiconductor storage
storage arrangement
charge barrier
barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888310760T
Other languages
English (en)
Other versions
DE3877525T2 (de
Inventor
Taiji Ema
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3877525D1 publication Critical patent/DE3877525D1/de
Publication of DE3877525T2 publication Critical patent/DE3877525T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/148—Silicon carbide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE8888310760T 1987-11-17 1988-11-15 Halbleiterspeicheranordnung mit einer ladungssperrschicht und verfahren zu ihrer herstellung. Expired - Fee Related DE3877525T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62288512A JPH06105774B2 (ja) 1987-11-17 1987-11-17 半導体記憶装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE3877525D1 true DE3877525D1 (de) 1993-02-25
DE3877525T2 DE3877525T2 (de) 1993-05-13

Family

ID=17731189

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888310760T Expired - Fee Related DE3877525T2 (de) 1987-11-17 1988-11-15 Halbleiterspeicheranordnung mit einer ladungssperrschicht und verfahren zu ihrer herstellung.

Country Status (5)

Country Link
US (1) US4961165A (de)
EP (1) EP0317257B1 (de)
JP (1) JPH06105774B2 (de)
KR (1) KR910009785B1 (de)
DE (1) DE3877525T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5156990A (en) * 1986-07-23 1992-10-20 Texas Instruments Incorporated Floating-gate memory cell with tailored doping profile
US5143861A (en) * 1989-03-06 1992-09-01 Sgs-Thomson Microelectronics, Inc. Method making a dynamic random access memory cell with a tungsten plug
US5270242A (en) * 1989-08-31 1993-12-14 Mitsubishi Denki Kabushiki Kaisha Method for fabricatins dynamic random access memory device having a capacitor for storing impact ionization charges
JPH03218666A (ja) * 1989-08-31 1991-09-26 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
US5114873A (en) * 1990-05-21 1992-05-19 Samsung Electronics Co., Ltd. Method for manufacturing a stacked capacitor DRAM cell
JP2564972B2 (ja) * 1990-06-18 1996-12-18 三菱電機株式会社 半導体記憶装置およびその製造方法
US5378650A (en) * 1990-10-12 1995-01-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a manufacturing method thereof
DE4134547C2 (de) * 1990-10-12 1994-01-20 Mitsubishi Electric Corp Isolationsstruktur für eine integrierte Halbleiterschaltung und Verfahren zur Herstellung derselben
JP3344485B2 (ja) * 1990-11-09 2002-11-11 富士通株式会社 半導体装置の製造方法
KR930010081B1 (ko) * 1991-05-24 1993-10-14 현대전자산업 주식회사 2중 적층캐패시터 구조를 갖는 반도체 기억장치 및 그 제조방법
US5428235A (en) * 1991-06-14 1995-06-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device including improved connection structure to FET elements
JPH05129554A (ja) * 1991-07-01 1993-05-25 Toshiba Corp ダイナミツク型半導体記憶装置
JP3375087B2 (ja) * 1991-10-21 2003-02-10 ローム株式会社 半導体記憶装置およびその記憶情報読出方法
JP2851753B2 (ja) * 1991-10-22 1999-01-27 三菱電機株式会社 半導体装置およびその製造方法
JPH0621447A (ja) * 1992-04-27 1994-01-28 Internatl Business Mach Corp <Ibm> 短チャネル電界効果トランジスタ
KR0139773B1 (ko) * 1992-08-11 1998-06-01 사또오 후미오 반도체 집적 회로 장치 및 그 제조 방법
US5599728A (en) * 1994-04-07 1997-02-04 Regents Of The University Of California Method of fabricating a self-aligned high speed MOSFET device
KR100190834B1 (ko) 1994-12-08 1999-06-01 다니구찌 이찌로오, 기타오카 다카시 반도체장치및그제조방법
JP3070420B2 (ja) * 1994-12-21 2000-07-31 日本電気株式会社 半導体装置の製造方法
US5930106A (en) * 1996-07-11 1999-07-27 Micron Technology, Inc. DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films
JP4056588B2 (ja) * 1996-11-06 2008-03-05 富士通株式会社 半導体装置及びその製造方法
US6159850A (en) * 1998-06-16 2000-12-12 United Microelectronics Corp. Method for reducing resistance of contact window
US6271107B1 (en) 1999-03-31 2001-08-07 Fujitsu Limited Semiconductor with polymeric layer
JP3348782B2 (ja) 1999-07-22 2002-11-20 日本電気株式会社 半導体装置の製造方法
US6780686B2 (en) * 2002-03-21 2004-08-24 Advanced Micro Devices, Inc. Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57188866A (en) * 1981-05-18 1982-11-19 Hitachi Ltd Manufacture of semiconductor device
US4506436A (en) * 1981-12-21 1985-03-26 International Business Machines Corporation Method for increasing the radiation resistance of charge storage semiconductor devices
JPS58209164A (ja) * 1982-05-31 1983-12-06 Toshiba Corp 不揮発性半導体メモリ装置の製造方法
JPS593964A (ja) * 1982-06-29 1984-01-10 Semiconductor Res Found 半導体集積回路
JPS5925242A (ja) * 1983-07-11 1984-02-09 Hitachi Ltd 半導体装置
JPS60113462A (ja) * 1983-11-25 1985-06-19 Fujitsu Ltd 半導体記憶装置
JPS60219764A (ja) * 1984-04-17 1985-11-02 Fujitsu Ltd 半導体装置の製造方法
JPS6212152A (ja) * 1985-07-09 1987-01-21 Nippon Denso Co Ltd 半導体装置の製造方法
JPS62142362A (ja) * 1985-12-17 1987-06-25 Matsushita Electronics Corp 不揮発性半導体記憶素子の製造方法
US4763181A (en) * 1986-12-08 1988-08-09 Motorola, Inc. High density non-charge-sensing DRAM cell

Also Published As

Publication number Publication date
KR910009785B1 (en) 1991-11-30
DE3877525T2 (de) 1993-05-13
JPH01130561A (ja) 1989-05-23
US4961165A (en) 1990-10-02
EP0317257B1 (de) 1993-01-13
EP0317257A2 (de) 1989-05-24
JPH06105774B2 (ja) 1994-12-21
KR890008988A (ko) 1989-07-13
EP0317257A3 (en) 1990-05-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee