DE3863376D1 - Materialien und verfahren zum aetzen von wolframpolyziden unter zuhilfenahme der silizide als maske. - Google Patents

Materialien und verfahren zum aetzen von wolframpolyziden unter zuhilfenahme der silizide als maske.

Info

Publication number
DE3863376D1
DE3863376D1 DE8888302403T DE3863376T DE3863376D1 DE 3863376 D1 DE3863376 D1 DE 3863376D1 DE 8888302403 T DE8888302403 T DE 8888302403T DE 3863376 T DE3863376 T DE 3863376T DE 3863376 D1 DE3863376 D1 DE 3863376D1
Authority
DE
Germany
Prior art keywords
etching
mask
rampolycides
tungste
silicides
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8888302403T
Other languages
English (en)
Inventor
Clark S Stone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Application granted granted Critical
Publication of DE3863376D1 publication Critical patent/DE3863376D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
DE8888302403T 1987-03-26 1988-03-18 Materialien und verfahren zum aetzen von wolframpolyziden unter zuhilfenahme der silizide als maske. Expired - Lifetime DE3863376D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/031,105 US4778563A (en) 1987-03-26 1987-03-26 Materials and methods for etching tungsten polycides using silicide as a mask

Publications (1)

Publication Number Publication Date
DE3863376D1 true DE3863376D1 (de) 1991-08-01

Family

ID=21857681

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888302403T Expired - Lifetime DE3863376D1 (de) 1987-03-26 1988-03-18 Materialien und verfahren zum aetzen von wolframpolyziden unter zuhilfenahme der silizide als maske.

Country Status (5)

Country Link
US (1) US4778563A (de)
EP (1) EP0284308B1 (de)
JP (1) JPS6477128A (de)
AT (1) ATE64797T1 (de)
DE (1) DE3863376D1 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112435A (en) * 1985-10-11 1992-05-12 Applied Materials, Inc. Materials and methods for etching silicides, polycrystalline silicon and polycides
US5007982A (en) * 1988-07-11 1991-04-16 North American Philips Corporation Reactive ion etching of silicon with hydrogen bromide
US5271799A (en) * 1989-07-20 1993-12-21 Micron Technology, Inc. Anisotropic etch method
US5201993A (en) * 1989-07-20 1993-04-13 Micron Technology, Inc. Anisotropic etch method
US5110411A (en) * 1990-04-27 1992-05-05 Micron Technology, Inc. Method of isotropically dry etching a poly/WSix sandwich structure
US5160408A (en) * 1990-04-27 1992-11-03 Micron Technology, Inc. Method of isotropically dry etching a polysilicon containing runner with pulsed power
US5077236A (en) * 1990-07-02 1991-12-31 Samsung Electronics Co., Ltd. Method of making a pattern of tungsten interconnection
JPH0496223A (ja) * 1990-08-03 1992-03-27 Fujitsu Ltd 半導体装置の製造方法
JP3127454B2 (ja) * 1990-08-08 2001-01-22 ソニー株式会社 シリコン系被エッチング材のエッチング方法
JPH0779102B2 (ja) * 1990-08-23 1995-08-23 富士通株式会社 半導体装置の製造方法
US5169487A (en) * 1990-08-27 1992-12-08 Micron Technology, Inc. Anisotropic etch method
JP3004699B2 (ja) * 1990-09-07 2000-01-31 東京エレクトロン株式会社 プラズマ処理方法
JP3729869B2 (ja) * 1990-09-28 2005-12-21 セイコーエプソン株式会社 半導体装置の製造方法
JP2964605B2 (ja) * 1990-10-04 1999-10-18 ソニー株式会社 ドライエッチング方法
US5094712A (en) * 1990-10-09 1992-03-10 Micron Technology, Inc. One chamber in-situ etch process for oxide and conductive material
US5160407A (en) * 1991-01-02 1992-11-03 Applied Materials, Inc. Low pressure anisotropic etch process for tantalum silicide or titanium silicide layer formed over polysilicon layer deposited on silicon oxide layer on semiconductor wafer
US5338398A (en) * 1991-03-28 1994-08-16 Applied Materials, Inc. Tungsten silicide etch process selective to photoresist and oxide
US5418188A (en) * 1991-09-05 1995-05-23 International Business Machines Corporation Method for controlled positioning of a compound layer in a multilayer device
US5358601A (en) * 1991-09-24 1994-10-25 Micron Technology, Inc. Process for isotropically etching semiconductor devices
US5332653A (en) * 1992-07-01 1994-07-26 Motorola, Inc. Process for forming a conductive region without photoresist-related reflective notching damage
US5188980A (en) * 1992-07-06 1993-02-23 United Microelectronics Corporation Inert gas purge for the multilayer poly gate etching improvement
JP2727966B2 (ja) * 1994-06-06 1998-03-18 日本電気株式会社 半導体装置の製造方法
EP0704886A1 (de) * 1994-09-29 1996-04-03 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Ätzverfahren für Kobalt-Silizid-Schichten
US5895255A (en) * 1994-11-30 1999-04-20 Kabushiki Kaisha Toshiba Shallow trench isolation formation with deep trench cap
US5529197A (en) * 1994-12-20 1996-06-25 Siemens Aktiengesellschaft Polysilicon/polycide etch process for sub-micron gate stacks
EP0731501A1 (de) * 1995-03-08 1996-09-11 International Business Machines Corporation Plasmaätzverfahren von einer Oxid/Polyzidstruktur
US5705433A (en) * 1995-08-24 1998-01-06 Applied Materials, Inc. Etching silicon-containing materials by use of silicon-containing compounds
US5874363A (en) * 1996-05-13 1999-02-23 Kabushiki Kaisha Toshiba Polycide etching with HCL and chlorine
EP0851479A1 (de) * 1996-12-24 1998-07-01 STMicroelectronics S.r.l. Verfahren zur Abscheidung einer dielektrischen Vielfachstruktur zur Verbesserung der Planarität von elektronischen Halbleitereinrichtungen
US6562724B1 (en) * 1997-06-09 2003-05-13 Texas Instruments Incorporated Self-aligned stack formation
EP0932190A1 (de) * 1997-12-30 1999-07-28 International Business Machines Corporation Plasmaätzverfahren der Wolframsilicidschicht bei der Herstellung von mehrschichtleitfähigem Gitter
US6436816B1 (en) * 1998-07-31 2002-08-20 Industrial Technology Research Institute Method of electroless plating copper on nitride barrier
KR100430950B1 (ko) * 1998-09-01 2004-06-16 엘지.필립스 엘시디 주식회사 박막트랜지스터 및 그 제조방법
TW501199B (en) 1999-03-05 2002-09-01 Applied Materials Inc Method for enhancing etching of TiSix
US7217652B1 (en) * 2000-09-21 2007-05-15 Spansion Llc Method of forming highly conductive semiconductor structures via plasma etch
WO2004079783A2 (en) * 2003-03-03 2004-09-16 Lam Research Corporation Method to improve profile control and n/p loading in dual doped gate applications
US7141505B2 (en) * 2003-06-27 2006-11-28 Lam Research Corporation Method for bilayer resist plasma etch
DE102005048366A1 (de) * 2005-10-10 2007-04-19 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von defektarmen selbstorganisierten nadelartigen Strukturen mit Nano-Dimensionen im Bereich unterhalb der üblichen Lichtwellenlängen mit großem Aspektverhältnis
WO2009067381A1 (en) * 2007-11-21 2009-05-28 Lam Research Corporation Method of controlling etch microloading for a tungsten-containing layer
JP7296912B2 (ja) * 2020-04-07 2023-06-23 東京エレクトロン株式会社 基板処理方法及び基板処理装置
DE102021116587B3 (de) 2021-06-28 2022-07-07 Jenoptik Optical Systems Gmbh Verfahren zum Herstellen einer Ätzmaske, Verfahren zum Ätzen einer Struktur in ein Substrat, Verwendung einer Tetrelschicht

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4422897A (en) * 1982-05-25 1983-12-27 Massachusetts Institute Of Technology Process for selectively etching silicon
NL8500771A (nl) * 1985-03-18 1986-10-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een op een laag siliciumoxide aanwezige dubbellaag - bestaande uit poly-si en een silicide - in een plasma wordt geetst.
US4613400A (en) * 1985-05-20 1986-09-23 Applied Materials, Inc. In-situ photoresist capping process for plasma etching
US4680086A (en) * 1986-03-20 1987-07-14 Motorola, Inc. Dry etching of multi-layer structures

Also Published As

Publication number Publication date
EP0284308A1 (de) 1988-09-28
US4778563A (en) 1988-10-18
JPS6477128A (en) 1989-03-23
ATE64797T1 (de) 1991-07-15
EP0284308B1 (de) 1991-06-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee