JPS6447025A - Etching - Google Patents

Etching

Info

Publication number
JPS6447025A
JPS6447025A JP20449587A JP20449587A JPS6447025A JP S6447025 A JPS6447025 A JP S6447025A JP 20449587 A JP20449587 A JP 20449587A JP 20449587 A JP20449587 A JP 20449587A JP S6447025 A JPS6447025 A JP S6447025A
Authority
JP
Japan
Prior art keywords
layer
patterned
layers
resist
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20449587A
Other languages
Japanese (ja)
Inventor
Hiroshi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP20449587A priority Critical patent/JPS6447025A/en
Publication of JPS6447025A publication Critical patent/JPS6447025A/en
Pending legal-status Critical Current

Links

Landscapes

  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To prevent an upper resist layer from being peeled at the time of developing of a lower resist layer by a method wherein the lower and upper resist layers are formed on a layer to be etched and after the upper resist layer is patterned, a substrate is heated and the lower resist layer is patterned. CONSTITUTION:An Al layer 2, which is used as a layer to be etched, is formed on a substrate 1 and thereafter, lower and upper resist layers 3 and 4 are formed. The layer 4 is patterned with ultraviolet lighted (UV). The layer 3 is exposed with far ultraviolet light (DUV) 5 using the layer 4 as a mask. The substrate 1 is subjected to heating treatment and the layer 3 is developed using the layer 4 as a mask and is patterned. The layer 2 is subjected to dry etching using the double resist layers consisting of the layers 3 and 4 as masks and is patterned and wiring layers 6 are formed.
JP20449587A 1987-08-18 1987-08-18 Etching Pending JPS6447025A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20449587A JPS6447025A (en) 1987-08-18 1987-08-18 Etching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20449587A JPS6447025A (en) 1987-08-18 1987-08-18 Etching

Publications (1)

Publication Number Publication Date
JPS6447025A true JPS6447025A (en) 1989-02-21

Family

ID=16491474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20449587A Pending JPS6447025A (en) 1987-08-18 1987-08-18 Etching

Country Status (1)

Country Link
JP (1) JPS6447025A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0595125A (en) * 1991-10-01 1993-04-16 Agency Of Ind Science & Technol Photoelectric conversion element
US8240914B1 (en) 1999-09-20 2012-08-14 Maverick Industries, Inc. Wireless remote cooking thermometer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0595125A (en) * 1991-10-01 1993-04-16 Agency Of Ind Science & Technol Photoelectric conversion element
US8240914B1 (en) 1999-09-20 2012-08-14 Maverick Industries, Inc. Wireless remote cooking thermometer system

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