JPS6427228A - Forming method for fine pattern of semiconductor element - Google Patents

Forming method for fine pattern of semiconductor element

Info

Publication number
JPS6427228A
JPS6427228A JP6917087A JP6917087A JPS6427228A JP S6427228 A JPS6427228 A JP S6427228A JP 6917087 A JP6917087 A JP 6917087A JP 6917087 A JP6917087 A JP 6917087A JP S6427228 A JPS6427228 A JP S6427228A
Authority
JP
Japan
Prior art keywords
resist
light
pattern
mask
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6917087A
Other languages
Japanese (ja)
Inventor
Takahiro Yamauchi
Hiroshi Otsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP6917087A priority Critical patent/JPS6427228A/en
Publication of JPS6427228A publication Critical patent/JPS6427228A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate an increase in a contact or a slit larger than a pattern on a mask due to the spread of a light by simultaneously performing the steps of removing an upper layer resist and developing a lower layer resist. CONSTITUTION:A lower layer resist 12 is formed on a base substrate 11, heated to volatilize solvent, thereby obtaining a thin CMS film. Then the resist 12 is coated by a rotary coating method with a positive resist to form an upper layer resist 14, thereby obtaining a film thickness of 1-2mum. Then, the resist 14 is patterned by a mask 15 by means of a lithography method with a UV light 16. Then, with the pattern of the resist 14 as a mask the pattern of the resist 14 is transferred to the CMS of the resist 14 simultaneously by exposure of a DUV (far ultraviolet ray) light 17. Then, the resist 14 is removed, the resist 12 is developed and an interlayer 13 is removed. Thus, the oversize of a slit or a contact does not occur due to the spread of the light.
JP6917087A 1987-03-25 1987-03-25 Forming method for fine pattern of semiconductor element Pending JPS6427228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6917087A JPS6427228A (en) 1987-03-25 1987-03-25 Forming method for fine pattern of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6917087A JPS6427228A (en) 1987-03-25 1987-03-25 Forming method for fine pattern of semiconductor element

Publications (1)

Publication Number Publication Date
JPS6427228A true JPS6427228A (en) 1989-01-30

Family

ID=13394970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6917087A Pending JPS6427228A (en) 1987-03-25 1987-03-25 Forming method for fine pattern of semiconductor element

Country Status (1)

Country Link
JP (1) JPS6427228A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333587B1 (en) * 1998-12-11 2001-12-25 Robert Bosch Gmbh Piezoelectric actuator
JP2010245131A (en) * 2009-04-01 2010-10-28 Jsr Corp Pattern forming method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333587B1 (en) * 1998-12-11 2001-12-25 Robert Bosch Gmbh Piezoelectric actuator
JP2010245131A (en) * 2009-04-01 2010-10-28 Jsr Corp Pattern forming method

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