JPS57141924A - Pattern forming method - Google Patents

Pattern forming method

Info

Publication number
JPS57141924A
JPS57141924A JP2651181A JP2651181A JPS57141924A JP S57141924 A JPS57141924 A JP S57141924A JP 2651181 A JP2651181 A JP 2651181A JP 2651181 A JP2651181 A JP 2651181A JP S57141924 A JPS57141924 A JP S57141924A
Authority
JP
Japan
Prior art keywords
layer
pattern
etching
az1350j
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2651181A
Other languages
Japanese (ja)
Inventor
Nobuhiro Endo
Yasuo Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2651181A priority Critical patent/JPS57141924A/en
Publication of JPS57141924A publication Critical patent/JPS57141924A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To form a fine mask pattern with high accuracy, by fluorine containing plasma treatment two layers of high molecular bond with its upper layer patterned by charged particles and thereby making the surface layer of one of the layers resistive to dry etching. CONSTITUTION:An Az1350J layer 103 for example is coated making the surface flat on an Si substrate 101 on which an oxide film, for example is formed. After forming a pattern by electron beam exposure providing, for example, a styrene resist layer 104, an dry-etching resistive modified layer 105 is formed on the patterned surface by exposing to a plasma of, for example, CF4. Then an oxygen plasma treatment is performed by a paralled flat plate type device, and a pattern consisting of the Az1350J layer 103 is formed utilizing the difference of etching speed, followed by oxide film etching. An organic material layer having vinyl base is formed in the lower layer and a negative resist pattern of PGMA and the like is formed in the upper layer and a positive type pattern is formed in the lower layer by a similar treatment. A fine pattern is thus formed not affected by side etching or proximity effect.
JP2651181A 1981-02-25 1981-02-25 Pattern forming method Pending JPS57141924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2651181A JPS57141924A (en) 1981-02-25 1981-02-25 Pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2651181A JPS57141924A (en) 1981-02-25 1981-02-25 Pattern forming method

Publications (1)

Publication Number Publication Date
JPS57141924A true JPS57141924A (en) 1982-09-02

Family

ID=12195498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2651181A Pending JPS57141924A (en) 1981-02-25 1981-02-25 Pattern forming method

Country Status (1)

Country Link
JP (1) JPS57141924A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895826A (en) * 1981-12-02 1983-06-07 Toppan Printing Co Ltd Forming method for pattern
JPS6132524A (en) * 1984-07-25 1986-02-15 Matsushita Electric Ind Co Ltd Pattern forming process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895826A (en) * 1981-12-02 1983-06-07 Toppan Printing Co Ltd Forming method for pattern
JPS6132524A (en) * 1984-07-25 1986-02-15 Matsushita Electric Ind Co Ltd Pattern forming process

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