JPS57211781A - Patterning method of double stacking thin film - Google Patents

Patterning method of double stacking thin film

Info

Publication number
JPS57211781A
JPS57211781A JP9787881A JP9787881A JPS57211781A JP S57211781 A JPS57211781 A JP S57211781A JP 9787881 A JP9787881 A JP 9787881A JP 9787881 A JP9787881 A JP 9787881A JP S57211781 A JPS57211781 A JP S57211781A
Authority
JP
Japan
Prior art keywords
etching
thin film
silicon
stacking thin
double stacking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9787881A
Other languages
Japanese (ja)
Other versions
JPH0151052B2 (en
Inventor
Mamoru Takeda
Hiroshi Yamazoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9787881A priority Critical patent/JPS57211781A/en
Publication of JPS57211781A publication Critical patent/JPS57211781A/en
Publication of JPH0151052B2 publication Critical patent/JPH0151052B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

PURPOSE:To pattern with good accuracy a double stacking thin film of silicon and silicon nitride by utilizing two kinds of etching solution having a great difference between etching speed for a etching-oriented film and that for no etching-oriented film. CONSTITUTION:A double stacking thin film provided in order of silicon nitride 2 and amorphous silicon 6 on a glass insulating substrate 5 is firstly patterned by photoresist. After that, the silicon 6 is etched by etching solution mixed hydrofluoric nitric acid and acetic acid with a volume percent of 6:1:2. Next, the silicon nitride 2 is etched by solution diluted 48% hydrogen fluoride with water at 1:10 or over. After finishing patterning in this way, unnecessary resist is removed.
JP9787881A 1981-06-24 1981-06-24 Patterning method of double stacking thin film Granted JPS57211781A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9787881A JPS57211781A (en) 1981-06-24 1981-06-24 Patterning method of double stacking thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9787881A JPS57211781A (en) 1981-06-24 1981-06-24 Patterning method of double stacking thin film

Publications (2)

Publication Number Publication Date
JPS57211781A true JPS57211781A (en) 1982-12-25
JPH0151052B2 JPH0151052B2 (en) 1989-11-01

Family

ID=14204000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9787881A Granted JPS57211781A (en) 1981-06-24 1981-06-24 Patterning method of double stacking thin film

Country Status (1)

Country Link
JP (1) JPS57211781A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62299035A (en) * 1986-06-18 1987-12-26 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS63293981A (en) * 1987-05-27 1988-11-30 Hitachi Ltd Manufacture of thin-film transistor
JPS6432635A (en) * 1987-07-22 1989-02-02 Alps Electric Co Ltd Manufacture of thin-film element substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62299035A (en) * 1986-06-18 1987-12-26 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS63293981A (en) * 1987-05-27 1988-11-30 Hitachi Ltd Manufacture of thin-film transistor
JPS6432635A (en) * 1987-07-22 1989-02-02 Alps Electric Co Ltd Manufacture of thin-film element substrate

Also Published As

Publication number Publication date
JPH0151052B2 (en) 1989-11-01

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