DE3579314D1 - Integrierte schaltungen. - Google Patents

Integrierte schaltungen.

Info

Publication number
DE3579314D1
DE3579314D1 DE8585308852T DE3579314T DE3579314D1 DE 3579314 D1 DE3579314 D1 DE 3579314D1 DE 8585308852 T DE8585308852 T DE 8585308852T DE 3579314 T DE3579314 T DE 3579314T DE 3579314 D1 DE3579314 D1 DE 3579314D1
Authority
DE
Germany
Prior art keywords
register
integrated circuit
circuits
clb
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585308852T
Other languages
English (en)
Inventor
William Laurence Knight
Mark Paraskeva
David Frank Burrows
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Semiconductor Ltd
Original Assignee
Plessey Overseas Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas Ltd filed Critical Plessey Overseas Ltd
Application granted granted Critical
Publication of DE3579314D1 publication Critical patent/DE3579314D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
DE8585308852T 1984-12-21 1985-12-05 Integrierte schaltungen. Expired - Lifetime DE3579314D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB848432533A GB8432533D0 (en) 1984-12-21 1984-12-21 Integrated circuits

Publications (1)

Publication Number Publication Date
DE3579314D1 true DE3579314D1 (de) 1990-09-27

Family

ID=10571663

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585308852T Expired - Lifetime DE3579314D1 (de) 1984-12-21 1985-12-05 Integrierte schaltungen.

Country Status (10)

Country Link
US (1) US4764926A (de)
EP (1) EP0195164B1 (de)
JP (1) JPH0660933B2 (de)
AT (1) ATE55837T1 (de)
AU (1) AU580362B2 (de)
DE (1) DE3579314D1 (de)
DK (1) DK166595B1 (de)
GB (1) GB8432533D0 (de)
GR (1) GR853067B (de)
IE (1) IE56976B1 (de)

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JP2641816B2 (ja) * 1991-07-23 1997-08-20 三菱電機株式会社 半導体集積回路の測定方法
US5422833A (en) * 1991-10-30 1995-06-06 Xilinx, Inc. Method and system for propagating data type for circuit design from a high level block diagram
US5258985A (en) * 1991-11-12 1993-11-02 Motorola, Inc. Combinational data generator and analyzer for built-in self test
US5412665A (en) * 1992-01-10 1995-05-02 International Business Machines Corporation Parallel operation linear feedback shift register
US5471481A (en) * 1992-05-18 1995-11-28 Sony Corporation Testing method for electronic apparatus
US5583786A (en) * 1993-12-30 1996-12-10 Intel Corporation Apparatus and method for testing integrated circuits
US5515384A (en) * 1994-03-01 1996-05-07 International Business Machines Corporation Method and system of fault diagnosis of application specific electronic circuits
US6070252A (en) * 1994-09-30 2000-05-30 Intel Corporation Method and apparatus for interactive built-in-self-testing with user-programmable test patterns
US5717702A (en) * 1995-03-14 1998-02-10 Hughes Electronics Scan testing digital logic with differing frequencies of system clock and test clock
US5684808A (en) * 1995-09-19 1997-11-04 Unisys Corporation System and method for satisfying mutually exclusive gating requirements in automatic test pattern generation systems
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JPH09166644A (ja) * 1995-12-18 1997-06-24 Nec Corp 半導体集積回路
JP3039362B2 (ja) * 1996-03-28 2000-05-08 日本電気株式会社 半導体集積論理回路のテストパターン作成方法
US6594789B2 (en) * 1997-09-16 2003-07-15 Texas Instruments Incorporated Input data capture boundary cell connected to target circuit output
US6260165B1 (en) 1996-10-18 2001-07-10 Texas Instruments Incorporated Accelerating scan test by re-using response data as stimulus data
US5936426A (en) * 1997-02-03 1999-08-10 Actel Corporation Logic function module for field programmable array
US5841790A (en) * 1997-04-08 1998-11-24 International Business Machines Corporation Apparatus for testing an adapter card ASIC with reconfigurable logic
US5844917A (en) * 1997-04-08 1998-12-01 International Business Machines Corporation Method for testing adapter card ASIC using reconfigurable logic
US5936976A (en) * 1997-07-25 1999-08-10 Vlsi Technology, Inc. Selecting a test data input bus to supply test data to logical blocks within an integrated circuit
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US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
DE19832307C2 (de) * 1998-07-17 2000-09-21 Siemens Ag Integrierte Schaltung mit einer Selbsttesteinrichtung
US6324664B1 (en) 1999-01-27 2001-11-27 Raytheon Company Means for testing dynamic integrated circuits
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
DE19948904C1 (de) * 1999-10-11 2001-07-05 Infineon Technologies Ag Schaltungszelle mit eingebauter Selbsttestfunktion und Verfahren zum Testen hierfür
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US6768684B2 (en) * 2002-01-25 2004-07-27 Sun Microsystems, Inc. System and method for small read only data
EP1357387A1 (de) * 2002-04-22 2003-10-29 Siemens Aktiengesellschaft Partial-BIST mit Erfassung der Verbindungen zwischen einzelnen Blöcken
US7308616B2 (en) * 2004-08-26 2007-12-11 International Business Machines Corporation Method, apparatus, and computer program product for enhanced diagnostic test error reporting utilizing fault isolation registers
JP5099869B2 (ja) * 2005-02-23 2012-12-19 ルネサスエレクトロニクス株式会社 半導体集積回路および半導体集積回路のテスト方法
JP2019045369A (ja) * 2017-09-05 2019-03-22 株式会社東芝 半導体装置およびその製造方法

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Also Published As

Publication number Publication date
US4764926A (en) 1988-08-16
IE56976B1 (en) 1992-02-26
GB8432533D0 (en) 1985-02-06
EP0195164B1 (de) 1990-08-22
JPS61155878A (ja) 1986-07-15
DK600185A (da) 1986-06-22
AU580362B2 (en) 1989-01-12
DK600185D0 (da) 1985-12-20
AU5109585A (en) 1986-06-26
EP0195164A1 (de) 1986-09-24
JPH0660933B2 (ja) 1994-08-10
ATE55837T1 (de) 1990-09-15
GR853067B (de) 1986-04-21
DK166595B1 (da) 1993-06-14
IE853221L (en) 1986-06-21

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: ROKE MANOR RESEARCH LTD., ROMSEY, HAMPSHIRE, GB

8328 Change in the person/name/address of the agent

Free format text: PRINZ, E., DIPL.-ING. LEISER, G., DIPL.-ING. SCHWEPFINGER, K., DIPL.-ING. BUNKE, H., DIPL.-CHEM. DR.RER.NAT. DEGWERT, H., DIPL.-PHYS., PAT.-ANWAELTE, 8000 MUENCHEN

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PLESSEY SEMICONDUCTORS LTD., SWINDON, WILTSHIRE, G

8327 Change in the person/name/address of the patent owner

Owner name: MITEL SEMICONDUCTOR LTD., SWINDON, WILTSHIRE, GB

8339 Ceased/non-payment of the annual fee