FR2432175A1 - Procede pour tester un systeme logique et systeme logique pour la mise en oeuvre de ce procede - Google Patents
Procede pour tester un systeme logique et systeme logique pour la mise en oeuvre de ce procedeInfo
- Publication number
- FR2432175A1 FR2432175A1 FR7822228A FR7822228A FR2432175A1 FR 2432175 A1 FR2432175 A1 FR 2432175A1 FR 7822228 A FR7822228 A FR 7822228A FR 7822228 A FR7822228 A FR 7822228A FR 2432175 A1 FR2432175 A1 FR 2432175A1
- Authority
- FR
- France
- Prior art keywords
- logic system
- testing
- phase
- implementing
- normal configuration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
Abstract
L'invention a pour objet un procédé pour tester un système logique dont les connexions internes ne sont pas accessibles depuis l'extérieur. Le procédé comprend plusieurs phases : une phase de contrôle de fonctionnement du système dans sa confi guration normale, une phase de test dans cette nouvelle configuration, une phase de restauration de la configuration normale. L'invention propose également un dispositif faisant application du procédé. Ce dispositif fait essentiellement appel à des bascules de forçage et/ou de prélèvement pour modifier les interconnexions logiques internes entre les opérateurs du système.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7822228A FR2432175A1 (fr) | 1978-07-27 | 1978-07-27 | Procede pour tester un systeme logique et systeme logique pour la mise en oeuvre de ce procede |
JP9516979A JPS5518800A (en) | 1978-07-27 | 1979-07-27 | Method for testing logic device and logic device |
DE19792930610 DE2930610A1 (de) | 1978-07-27 | 1979-07-27 | Verfahren zum ueberpruefen eines datenverarbeitungssystemes und datenverarbeitungssystem zur durchfuehrung des verfahrens |
US06/267,347 US4423509A (en) | 1978-07-27 | 1981-05-26 | Method of testing a logic system and a logic system for putting the method into practice |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7822228A FR2432175A1 (fr) | 1978-07-27 | 1978-07-27 | Procede pour tester un systeme logique et systeme logique pour la mise en oeuvre de ce procede |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2432175A1 true FR2432175A1 (fr) | 1980-02-22 |
FR2432175B1 FR2432175B1 (fr) | 1981-01-09 |
Family
ID=9211240
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7822228A Granted FR2432175A1 (fr) | 1978-07-27 | 1978-07-27 | Procede pour tester un systeme logique et systeme logique pour la mise en oeuvre de ce procede |
Country Status (4)
Country | Link |
---|---|
US (1) | US4423509A (fr) |
JP (1) | JPS5518800A (fr) |
DE (1) | DE2930610A1 (fr) |
FR (1) | FR2432175A1 (fr) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4502127A (en) * | 1982-05-17 | 1985-02-26 | Fairchild Camera And Instrument Corporation | Test system memory architecture for passing parameters and testing dynamic components |
US4556976A (en) * | 1982-08-14 | 1985-12-03 | International Computers Limited | Checking sequential logic circuits |
US4513418A (en) * | 1982-11-08 | 1985-04-23 | International Business Machines Corporation | Simultaneous self-testing system |
US4495629A (en) * | 1983-01-25 | 1985-01-22 | Storage Technology Partners | CMOS scannable latch |
US4534028A (en) * | 1983-12-01 | 1985-08-06 | Siemens Corporate Research & Support, Inc. | Random testing using scan path technique |
GB8432533D0 (en) * | 1984-12-21 | 1985-02-06 | Plessey Co Plc | Integrated circuits |
US4635261A (en) * | 1985-06-26 | 1987-01-06 | Motorola, Inc. | On chip test system for configurable gate arrays |
US4749947A (en) * | 1986-03-10 | 1988-06-07 | Cross-Check Systems, Inc. | Grid-based, "cross-check" test structure for testing integrated circuits |
US5065090A (en) * | 1988-07-13 | 1991-11-12 | Cross-Check Technology, Inc. | Method for testing integrated circuits having a grid-based, "cross-check" te |
DE3886529T2 (de) * | 1988-08-27 | 1994-06-30 | Ibm | Einrichtung in einem Datenverarbeitungssystem zur System-Initialisierung und -Rückstellung. |
NL8900151A (nl) * | 1989-01-23 | 1990-08-16 | Philips Nv | Werkwijze voor het testen van een schakeling, alsmede schakeling geschikt voor een dergelijke werkwijze. |
JP3118266B2 (ja) * | 1990-03-06 | 2000-12-18 | ゼロックス コーポレイション | 同期セグメントバスとバス通信方法 |
US5166604A (en) * | 1990-11-13 | 1992-11-24 | Altera Corporation | Methods and apparatus for facilitating scan testing of asynchronous logic circuitry |
US5528600A (en) * | 1991-01-28 | 1996-06-18 | Actel Corporation | Testability circuits for logic arrays |
US5648661A (en) * | 1992-07-02 | 1997-07-15 | Lsi Logic Corporation | Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies |
US5389556A (en) * | 1992-07-02 | 1995-02-14 | Lsi Logic Corporation | Individually powering-up unsingulated dies on a wafer |
US5442282A (en) * | 1992-07-02 | 1995-08-15 | Lsi Logic Corporation | Testing and exercising individual, unsingulated dies on a wafer |
US5532174A (en) * | 1994-04-22 | 1996-07-02 | Lsi Logic Corporation | Wafer level integrated circuit testing with a sacrificial metal layer |
US6157210A (en) | 1997-10-16 | 2000-12-05 | Altera Corporation | Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits |
DE102005009955A1 (de) * | 2005-03-04 | 2006-09-07 | Bayerische Motoren Werke Ag | Verfahren und Vorrichtung zum Überwachen eines Ablaufs einer Rechenvorrichtung |
KR100825013B1 (ko) * | 2006-09-28 | 2008-04-24 | 주식회사 하이닉스반도체 | 패키지 레벨의 명령 테스트를 위한 반도체 장치 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2177791A1 (fr) * | 1972-03-27 | 1973-11-09 | Ibm | |
FR2330014A1 (fr) * | 1973-05-11 | 1977-05-27 | Ibm France | Procede de test de bloc de circuits logiques integres et blocs en faisant application |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3815025A (en) * | 1971-10-18 | 1974-06-04 | Ibm | Large-scale integrated circuit testing structure |
US3789205A (en) * | 1972-09-28 | 1974-01-29 | Ibm | Method of testing mosfet planar boards |
US3784907A (en) * | 1972-10-16 | 1974-01-08 | Ibm | Method of propagation delay testing a functional logic system |
US3761695A (en) * | 1972-10-16 | 1973-09-25 | Ibm | Method of level sensitive testing a functional logic system |
US3961251A (en) * | 1974-12-20 | 1976-06-01 | International Business Machines Corporation | Testing embedded arrays |
US3961252A (en) * | 1974-12-20 | 1976-06-01 | International Business Machines Corporation | Testing embedded arrays |
US3961254A (en) * | 1974-12-20 | 1976-06-01 | International Business Machines Corporation | Testing embedded arrays |
US4051352A (en) * | 1976-06-30 | 1977-09-27 | International Business Machines Corporation | Level sensitive embedded array logic system |
JPS5352029A (en) * | 1976-10-22 | 1978-05-12 | Fujitsu Ltd | Arithmetic circuit unit |
-
1978
- 1978-07-27 FR FR7822228A patent/FR2432175A1/fr active Granted
-
1979
- 1979-07-27 JP JP9516979A patent/JPS5518800A/ja active Granted
- 1979-07-27 DE DE19792930610 patent/DE2930610A1/de not_active Ceased
-
1981
- 1981-05-26 US US06/267,347 patent/US4423509A/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2177791A1 (fr) * | 1972-03-27 | 1973-11-09 | Ibm | |
FR2330014A1 (fr) * | 1973-05-11 | 1977-05-27 | Ibm France | Procede de test de bloc de circuits logiques integres et blocs en faisant application |
Also Published As
Publication number | Publication date |
---|---|
JPS6258024B2 (fr) | 1987-12-03 |
DE2930610A1 (de) | 1980-02-07 |
FR2432175B1 (fr) | 1981-01-09 |
US4423509A (en) | 1983-12-27 |
JPS5518800A (en) | 1980-02-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |