DE3583590D1 - Testsystem fuer eine tastaturschnittstellenschaltung. - Google Patents

Testsystem fuer eine tastaturschnittstellenschaltung.

Info

Publication number
DE3583590D1
DE3583590D1 DE8585113177T DE3583590T DE3583590D1 DE 3583590 D1 DE3583590 D1 DE 3583590D1 DE 8585113177 T DE8585113177 T DE 8585113177T DE 3583590 T DE3583590 T DE 3583590T DE 3583590 D1 DE3583590 D1 DE 3583590D1
Authority
DE
Germany
Prior art keywords
interface circuit
shift register
test system
trouble
keyboard interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585113177T
Other languages
English (en)
Inventor
Yoshihisa Sueta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3583590D1 publication Critical patent/DE3583590D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Input From Keyboards Or The Like (AREA)
DE8585113177T 1984-12-14 1985-10-17 Testsystem fuer eine tastaturschnittstellenschaltung. Expired - Fee Related DE3583590D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59263156A JPS61141022A (ja) 1984-12-14 1984-12-14 キ−ボ−ド・インタ−フエ−ス回路の試験装置

Publications (1)

Publication Number Publication Date
DE3583590D1 true DE3583590D1 (de) 1991-08-29

Family

ID=17385572

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585113177T Expired - Fee Related DE3583590D1 (de) 1984-12-14 1985-10-17 Testsystem fuer eine tastaturschnittstellenschaltung.

Country Status (4)

Country Link
US (1) US4692691A (de)
EP (1) EP0184639B1 (de)
JP (1) JPS61141022A (de)
DE (1) DE3583590D1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365165A (en) * 1986-09-19 1994-11-15 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US4947395A (en) * 1989-02-10 1990-08-07 Ncr Corporation Bus executed scan testing method and apparatus
US5228045A (en) * 1990-08-06 1993-07-13 Ncr Corporation Test driver for connecting a standard test port integrated circuit chip to a controlling computer
US5528600A (en) * 1991-01-28 1996-06-18 Actel Corporation Testability circuits for logic arrays
US5471153A (en) * 1991-04-26 1995-11-28 Vlsi Technologies, Inc. Methods and circuits for testing open collectors and open drains
US5581693A (en) * 1993-07-14 1996-12-03 Dell Usa, L.P. Method and apparatus for inhibiting computer interface clocks during diagnostic testing
DE19822389A1 (de) 1998-05-19 1999-11-25 Hoogovens Aluminium Profiltech Biegevorrichtung
CN1885272B (zh) * 2005-06-25 2010-05-26 鸿富锦精密工业（深圳）有限公司 Ps/2接口的检测装置与方法
US7366597B2 (en) * 2005-07-22 2008-04-29 Gm Global Technology Operations, Inc. Validating control system software variables
TWI438454B (zh) * 2011-12-22 2014-05-21 Wistron Corp 鍵盤自動測試方法及應用其之鍵盤自動測試系統

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8004176A (nl) * 1980-07-21 1982-02-16 Philips Nv Inrichting voor het testen van een schakeling met digitaal werkende en kombinatorisch werkende onderdelen.
US4500836A (en) * 1980-10-31 1985-02-19 Pacific Western Systems, Inc. Automatic wafer prober with programmable tester interface
US4503387A (en) * 1982-12-30 1985-03-05 Harris Corporation A.C. Testing of logic arrays
DE3313449C2 (de) * 1983-04-13 1987-01-02 Computer Gesellschaft Konstanz Mbh, 7750 Konstanz Vorrichtung zum Prüfen von Flachbaugruppen

Also Published As

Publication number Publication date
JPS61141022A (ja) 1986-06-28
JPH0378647B2 (de) 1991-12-16
US4692691A (en) 1987-09-08
EP0184639A2 (de) 1986-06-18
EP0184639B1 (de) 1991-07-24
EP0184639A3 (en) 1988-06-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee