JPS6413478A - Test system for integrated circuit - Google Patents

Test system for integrated circuit

Info

Publication number
JPS6413478A
JPS6413478A JP62170450A JP17045087A JPS6413478A JP S6413478 A JPS6413478 A JP S6413478A JP 62170450 A JP62170450 A JP 62170450A JP 17045087 A JP17045087 A JP 17045087A JP S6413478 A JPS6413478 A JP S6413478A
Authority
JP
Japan
Prior art keywords
signal
inputted
data
synchronism
clearing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62170450A
Other languages
Japanese (ja)
Inventor
Nobukazu Kirigatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62170450A priority Critical patent/JPS6413478A/en
Publication of JPS6413478A publication Critical patent/JPS6413478A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To secure data being tested by limiting the supply of a clear signal outputted from a clearing means to a FF by a clearing control means. CONSTITUTION:Scan-in data A is inputted to the SI terminal of a FF 241 from the outside of a LSI 201 in synchronism with a scan clock signal SC. This data A is latched by a FF 243 in synchronism with a next signal SC. Similarly, the data A is shifted to FFs 211...247 in synchronism with a sequential signal SC. Then test data is inputted to the input pin of the LSI 201 and operation is advanced by one cycle in synchronism with the signal SC. At this time, a clearing control signal 0 is inputted to a 2nd input terminal of a NAND gate 221. When the operation is advanced by one cycle, a clearing signal inputted to the D terminal of the FF 211 is latched and inputted to a 1st input terminal of a gate 221. The gate 221, however, outputs 1 as long as the clearing control signal is 0, so the FFs 231 and 233 are not cleared.
JP62170450A 1987-07-08 1987-07-08 Test system for integrated circuit Pending JPS6413478A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62170450A JPS6413478A (en) 1987-07-08 1987-07-08 Test system for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62170450A JPS6413478A (en) 1987-07-08 1987-07-08 Test system for integrated circuit

Publications (1)

Publication Number Publication Date
JPS6413478A true JPS6413478A (en) 1989-01-18

Family

ID=15905155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62170450A Pending JPS6413478A (en) 1987-07-08 1987-07-08 Test system for integrated circuit

Country Status (1)

Country Link
JP (1) JPS6413478A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2455190A1 (en) * 1979-04-23 1980-11-21 Nissan Motor METHOD AND APPARATUS FOR CONTROLLING A SPARK TRIGGER IN AN IGNITION SYSTEM FOR AN ENGINE USING EXHAUST GAS RECYCLING

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6291871A (en) * 1985-10-18 1987-04-27 Fujitsu Ltd Diagnostic system for synchronizing and asynchronizing circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6291871A (en) * 1985-10-18 1987-04-27 Fujitsu Ltd Diagnostic system for synchronizing and asynchronizing circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2455190A1 (en) * 1979-04-23 1980-11-21 Nissan Motor METHOD AND APPARATUS FOR CONTROLLING A SPARK TRIGGER IN AN IGNITION SYSTEM FOR AN ENGINE USING EXHAUST GAS RECYCLING

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