DE112004001041B4 - Verfahren zur Herstellung eines Halbleiterbauelements umfassend ein chemisch-mechanisches Mehrschrittpolierverfahren für einen Gatebereich in einem FINFET - Google Patents

Verfahren zur Herstellung eines Halbleiterbauelements umfassend ein chemisch-mechanisches Mehrschrittpolierverfahren für einen Gatebereich in einem FINFET Download PDF

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Publication number
DE112004001041B4
DE112004001041B4 DE112004001041T DE112004001041T DE112004001041B4 DE 112004001041 B4 DE112004001041 B4 DE 112004001041B4 DE 112004001041 T DE112004001041 T DE 112004001041T DE 112004001041 T DE112004001041 T DE 112004001041T DE 112004001041 B4 DE112004001041 B4 DE 112004001041B4
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Prior art keywords
gate structure
gate
semiconductor device
cmp
forming
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Expired - Fee Related
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DE112004001041T
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German (de)
English (en)
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DE112004001041T5 (de
Inventor
Krishnashree San Ramon Achuthan
Shibly S. San Jose Ahmed
Haihong Milpitas Wang
Bin Cupertino Yu
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09GPOLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00Polishing compositions
    • C09G1/02Polishing compositions containing abrasives or grinding agents
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0243Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40Chemomechanical polishing [CMP]
    • H10P52/403Chemomechanical polishing [CMP] of conductive or resistive materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06Planarisation of inorganic insulating materials
    • H10P95/062Planarisation of inorganic insulating materials involving a dielectric removal step
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739Conductor-insulator-semiconductor electrodes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/959Mechanical polishing of wafer

Landscapes

  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
DE112004001041T 2003-06-12 2004-06-05 Verfahren zur Herstellung eines Halbleiterbauelements umfassend ein chemisch-mechanisches Mehrschrittpolierverfahren für einen Gatebereich in einem FINFET Expired - Fee Related DE112004001041B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/459,495 US6855607B2 (en) 2003-06-12 2003-06-12 Multi-step chemical mechanical polishing of a gate area in a FinFET
US10/459,495 2003-06-12
PCT/US2004/017724 WO2004112105A2 (en) 2003-06-12 2004-06-05 Multi-step chemical mechanical polishing of a gate area in a finfet

Publications (2)

Publication Number Publication Date
DE112004001041T5 DE112004001041T5 (de) 2006-04-20
DE112004001041B4 true DE112004001041B4 (de) 2010-04-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE112004001041T Expired - Fee Related DE112004001041B4 (de) 2003-06-12 2004-06-05 Verfahren zur Herstellung eines Halbleiterbauelements umfassend ein chemisch-mechanisches Mehrschrittpolierverfahren für einen Gatebereich in einem FINFET

Country Status (8)

Country Link
US (2) US6855607B2 (https=)
JP (1) JP2007500456A (https=)
KR (1) KR101062986B1 (https=)
CN (1) CN1806318B (https=)
DE (1) DE112004001041B4 (https=)
GB (1) GB2419232B (https=)
TW (1) TWI353011B (https=)
WO (1) WO2004112105A2 (https=)

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Also Published As

Publication number Publication date
US6855607B2 (en) 2005-02-15
WO2004112105A3 (en) 2005-02-24
US7125776B2 (en) 2006-10-24
KR101062986B1 (ko) 2011-09-07
GB2419232A (en) 2006-04-19
TWI353011B (en) 2011-11-21
KR20060020674A (ko) 2006-03-06
CN1806318B (zh) 2010-05-12
GB0526386D0 (en) 2006-02-08
DE112004001041T5 (de) 2006-04-20
JP2007500456A (ja) 2007-01-11
GB2419232B (en) 2007-01-17
TW200520081A (en) 2005-06-16
WO2004112105A2 (en) 2004-12-23
CN1806318A (zh) 2006-07-19
US20050118824A1 (en) 2005-06-02
US20040253775A1 (en) 2004-12-16

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