TWI353011B - Multi-step chemical mechanical polishing of a gate - Google Patents

Multi-step chemical mechanical polishing of a gate Download PDF

Info

Publication number
TWI353011B
TWI353011B TW093116517A TW93116517A TWI353011B TW I353011 B TWI353011 B TW I353011B TW 093116517 A TW093116517 A TW 093116517A TW 93116517 A TW93116517 A TW 93116517A TW I353011 B TWI353011 B TW I353011B
Authority
TW
Taiwan
Prior art keywords
layer
gate
slurry
fin
polysilicon layer
Prior art date
Application number
TW093116517A
Other languages
English (en)
Other versions
TW200520081A (en
Inventor
Krishnashree Achuthan
Shibly S Ahmed
Haihong Wang
Bin Yu
Original Assignee
Globalfoundries Us Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Us Inc filed Critical Globalfoundries Us Inc
Publication of TW200520081A publication Critical patent/TW200520081A/zh
Application granted granted Critical
Publication of TWI353011B publication Critical patent/TWI353011B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09G—POLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00—Polishing compositions
    • C09G1/02—Polishing compositions containing abrasives or grinding agents
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/959—Mechanical polishing of wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體裝置和製造半導體裝置之方法。 本發明係對雙閘極裝置（(1〇111316-83士6(16乂46)有特別的適 用性。 【先前技術】 - 由於逐漸高升之高密度與高性能之需求，對超大積體 電路（ultra large integration)半導體裝置（device)有關 之设s十特徵，就像閘極長度’需求1 〇〇奈米（nan〇meter ; 修 nm)以下’高可靠度（reiiabinty)以及製造產率 (throughput)之增加。縮小設計特徵在ι〇〇奈米以下將對 傳統的製造方式極限是一種挑戰。 例如，當傳統平坦的金屬氧化物半導體場效電晶體 (M0SFET)的閘極長度尺寸在i〇〇nm以下時，短通道效應 (short channel effect)之問題則伴隨而來，而如在源極 (source)與閘極（drain)之間有過多的漏電流（ieakage)等 問題很難克服。除此之外，電子移動率（mQbiiity)的下降 與-些製程上的問題也都將造成傳統的金屬氧化半導體場 效電晶體在尺寸上其包含元件特徵逐漸縮小化之困難。為 了要促進場效電晶體（FET)的性能與可以使元件尺寸縮小 化，因此要探究新的元件結構。 雙開極（doubl
儿观干等體場效電晶體 I存之平坦之M0SFET結 雙閘極的M0SFET比傳統 92632修正本 5 的原料矽（conventional bulk silicon)之 MOSFET 提供更 好的特性質。這些改進產生於因雙閘極的M〇SFET在通道的 兩側各具有一個閘極，而不是像傳統的M〇SFET只有一個閘 極在其通道一側。當有兩個閘極時，則將由汲極（drain) 所產生之電場從通道之源極（s〇urce )端遮開有較好效杲 (screened)。同樣地，兩個閘極比起單一閘極大體上能控 制兩倍多的電流，這樣的結果將造成較強的交換訊號 (switching signal)。 &鰭狀場效電晶體（FinFET)是近來顯現優良的短通道性 能（short channel behavior)之雙閘極結構。FinFET 是包 含形成於-個垂直的鰭形電場裡之通冑。韓狀場效電晶體 可使用那些用來製造傳統平坦的M〇SFET之佈局（丨町仙〇 與製程技術製造出來。 【發明内容】 本發明之實施例提供-種具有控制極為細微之閉極區 域之雙閘極的M0SFET。 、本發明的一局面提供一種製造半導體裝置之方法。此 方法包含在絕緣材料（insulat〇r)Ji形成韓狀結構並至少 在部分的轉狀結構和部份的絕緣材料之上形成間極結構。 ^方法更進一步包含使用第一研磨液⑹町〇來執行化學 ⑽:磨（chemical mechanical p〇llsh;gpCMp)閑極的 ^構錯以平坦閘極結構和使用不同於第一研磨液的第二研 磨液來執行閘極結構的CMp藉以平坦閘極結構。第二次閘 極結構的平坦化降低鰭形結構上面之祕結構之高度而^ 92632修正本 6 方面提向鰭形結構周圍之間極結構高度。 本發明的另一局面提供形成一個MOSFET的方法。此方 =含在—絕緣層（insulatQrlayer)上形成源極、沒極和 ”曰无構。部分的鰭形結構充當作MOSFET的通道。此方法 f推一牛勺a丄 ^ nx ^匕s在鰭形結構的側面形成介電層（diekctric 並在介電層的周圍沉積—多晶石夕層（PQlySilicon layer)。此多晶矽層充當作在m〇sfet的閘極區域。再更進 此方法包含以第—料平坦化多W層和以比在 弟-速率更慢的第二速率更進一步平坦化多晶矽層。 【實施方式】 [執行發明的最佳模式] 以下參照附圖詳細說明本發明。在不同圖上的相同未 考^虎表示相同或相似的元件。當然下面詳細的描述並不 限疋本發明。本發明之範圍係由附件之申請專利範圍及里 等效技術來界宏。 ' 指一 通道 本文中所稱之鰭狀場效電晶體FinFET，專有名詞，係 種型式之MOSFET ’就是在垂直的石夕，，韓，，趣形成一傳導 。這種FinFET為從所周知的技術。 第1圖表示根據本發明的具體實例而形成的半導體裝 置1()0。參照第11，半導體裝置刚可包含絕緣層上有、 矽（silicon on insulat〇r ;即s〇I)之結構，而苴中包含 石夕基材no、埋藏氧化物層12G(BuriedQxide)和在埋藏氧 化物層⑵上方之㈣13〇。以傳統的方式可切基材ιι〇 上形成埋藏氧化物層120與;ε夕層13〇。 92632修正本 7 .-S5S01-1 —------------ 知“ .r〜 r~f ·，· w ^-—-^-- 在一個模範的完成例子裡，埋藏氧化物層120可包含 氧化矽其厚度範圍大約從1〇〇〇 A至3〇〇〇人。矽層13〇可 包含單晶（monocrystalline)或多晶（polycrystalHne) 矽。矽層1 30是作為雙閘極電晶體裝置中用來形成鰭狀結 構’正如以下有更詳細之描述。 另與本發明有關之選擇性實施例，基材1 1 〇與石夕層 U0可包含其他半導體物質，就像鍺化打随“⑽），或複二 半導體材料，就像矽-鍺。而埋藏氧化層120亦可包含其他 電材料。 在石夕層130上可形成介電層14〇，如氮化石夕層或氧化 —S (例如，Si〇2) ’俾以充當再隨後蝕刻製程其間之保護 cap)。在一個示範的實施例子裡，介電層 〇可成長之厚度範圍大約從15〇人至7〇〇 A。接下來， :將光阻劑材料沉積並形成為續後的加工 光阻劑光罩15〇(photoresist mas ΰ案之 來沉積並圖案化光阻劑。ask)可用任何傳統方式 在一個後Γ㈣半導縣置_並料光阻劑光罩150。 - ^不乾的實施例子裡，可用傳統方式來钱刻石夕層 3，在，氧化物層12"止钱刻 狀物形成之後，可在相鄰於各自 "勿，在- 極與汲極區域。例如，在— \^上形成源 統方式來沉積、圖案化與姓刻:夕：施例子裡，可用傳 俾以形成源極與汲極區域 層或複合的石夕錯層 刻石夕η 士 ^在他靶例裡，可圖案化與蝕 丨夕層13“同時形成源極與及極範圍並具有鳄狀物。 92632修正本 8 F3*5*3011 · —- 第2A圖概略圖示以上述方法形成半導體裝置1〇〇上之 鰭狀結構之上視圖。根據本發明之具體實施例，可在埋藏 氧化物層120上相鄰於鰭狀物21 〇之端部形成源極區域 220與汲極230區域。 第2B圖是由第2A圖中沿著A_A，線之橫截面圖，其圖 解說明鰭狀結構210之形成。如上所述，蝕刻介電層 與矽層130以形成具有介電蓋14〇(dielectric cap)之鰭 狀物210。 θ 第3圖為根據本發明之一具體實施例之截面圖表示閘 極介電層（gate dlelectric layer)與覆蓋在鰭狀物21〇 上的閘極材料（gate material)之形成。在鰭狀物21〇上可 形成一介電層。例如，在鰭狀物21〇上以熱處理成長出一 薄的犧牲氧化物膜310(sacrificial〇xideiilm)，如第3 圖所示。這氧化物膜成長之厚度範圍大約從5〇人至ι〇〇λ 並且在鰭狀物210之曝露一側的表面上形成。 氧化物膜310形成之後，可在半導體裝置1〇〇上沉積 閘極材料層320。在-個示範的實施例子裡，間極材料層 320可包含用傳統的化學氣相沉積法（CVD)或其他已知的 技術沉積的多晶矽。沉積出來的閘極材料320其厚度範圍 大約從500又至2800 A。其他一些可選擇的半導體材料， 如錯或石夕與錯之複合材料或各種金屬材料也可用來作閉極 材料閑極材料層320形成韓狀場效電晶體⑻哪了）⑽ 的導電性閘極。 如第3圖所示，閘極材料層32〇在鰭狀21〇上方之區 92632修正本 9 ° ，…、j 域作垂直延伸。在—彳gl + m n — 個不乾的貫施例子裡，閘極村料層320 延伸一距離！】，其範圍可為大致從5〇〇 Α至15〇〇入。 而閘極材料層32〇可被平坦化。與本發明之一局面一 致地’可藉由多步驟平坦化製程平坦閘極材料層⑽。 化干機械研磨（CMP)為眾所週知的平坦化技術，為一般 用來平坦化半導體表面。在化學機械研磨程 圓（wafer)面朝下放 τ , 放置在方疋轉平台（rotating platen) 而將晶圓保持在承载體（carrier)上，並以相同於旋轉 平台之旋轉方向旋轉。在平台表面設有一個研磨塾 p ing pad)，並於其上有研磨液（slurry)。此研磨液 可包含在承載溶液（earrier SQiut⑽）财二氧化石夕顆粒 ^ PartlCles)㈣體溶液（colloidal s〇lution)。 研磨液的化學組成與其酸驗值（pH)將影響化學機械研磨製 程的效能。 第4A圖為表示根據與本發明一致之可實施平坦化妒 程之第一步驟說明閘極材料320之平坦化之橫截面圖。： 此步驟’可實行，，粗略的，，平坦化。換言之，可在此製程對 =極材枓3 2 0相對地以高移除率作快速研磨一部分的間極 、科320。在一可實施的例子裡’在粗平坦化之間其一部 ^的閉極材料320可減少，正如第4圖所示。例如，閘亟 、料320之里可移除，而使距離“之閉極材料⑽之量之 成為大約從〇 A至j λ μ ^。 至1500 Α之靶圍。而距離h之範圍可從 、八至500 A。此粗平坦化步驟可降低在鰭狀上方部 /刀和閘極材料3 2 〇之周圍區域的閘極材料高度。 92632修正本 10 未 3 53011 ---- (? r ·.« ·.；
如第4Α圖所不在此平坦化中使用多晶矽研磨液 slurry)將有大約從10.5至115之酸鹼值（pH)範圍^此研 磨液為以二氧化矽基底之緩衝研磨液（siiica based buffered Slurry)其内有加入額外的鹼性成分（aikaH C〇mP〇nent)，就如四甲基氫氧化銨（Tetra Methyl Ammonium Hydroxide ’ TMAH)、氫氧化銨或氫氧化鉀，其濃度範圍大 約從0. 1%至4% 。 第4B圖為橫截面圖其根據與本發明一致之可實施平 坦化製程之第二步驟說明閘極材料32〇之平坦化。在此步 驟，可實行精細的平坦化。換言之，在執行此製程之平扭 7速率相對於第-步的研磨速率來的低。例如，使用此製 =將X近乎 A/分鐘之速率研磨間極材料32〇。執行此 i程研磨閘極材謂直至閘極材料32〇仍有近乎_八 保留在鰭狀物21 〇的上方為止，如第 第4B圖所示為14。 如弟則所不。此距離如 第Γ步驟的平坦化製程裡，所選定之研磨液除了能 達成低研磨群（lQWer pQlishing咖）的要求之外 =ΐΓΓΓ32°較低的區域上。例如，研磨㈣ 已I、有疏水性(hydrophobi C)分子團之 :::的化合物有附著在多—料層‘ 之：：Γ化製程將有提高間極材料層320較低的區域 二。有助材料層3平 士-化⑽_極材制⑽㈣果是相當㈣ = 好的平面—致性（uniformity)。 才田 Π 92632修正本 ^53011 ------ 液其酸鹼值範圍大約在 二氧化矽為基底之緩衝研 就如四甲基氫氧化銨 其濃度範圍大約從〇. J % 使用在第二步平坦化的研磨 10. 5至11. 5之間。研磨液是以 磨液，而具有額外的驗性成分， (TMHA)、氫氧化銨或氫氧化奸， 至1% 。 如上所討論到的多步驟伞士 夕/鄉十坦化步驟將容許得到一個冥 度可控制的CMP製程’這樣的製程能保留如_入這麼； ❿ 之覆蓋在韓狀物210之上的閘極材料32〇層。第一 相對高速率研磨製程以平扫最初邱八 乂 疋 ★ 丁 —取初。卩分的閘極材料320層而 弟一步驟則是降低移除速率俾以遠士、链也Λ 、千佴以違成鰭狀物21〇上閘極材 料320層之所需要之量。雖然於此
'於此私別地描述二步驟的CMP 衣程’但熟悉此項技術者可以了解到將能❹超過 以上的製程。 /哪 第5圖為概略表示半導體裝置1〇〇之上視圖，表示從 閘極材料320層上圖案化一閘極結構51〇。在完成⑶ 程之後可圖案化及蝕刻閘極結構51〇。閘極結構5ι〇延= 橫跨過鰭狀210的通道區域。閘極結構51〇可包含具有鄰 接於鰭狀210的側邊之閘極區域和與鰭狀21〇物隔開之大 電極部分。閘極結構51〇的電極部分可提供可使用的電接 站（electrical contact)作為偏壓（biasing)與其他閘極 部分之控制之用。 之後可摻雜源極/汲極220與230之區域。例如，在源 極八及極2 2 0與2 3 0之區域裡將n型或p型的雜質植入其 内。基於特定之完成品之裝置之需要可選定特殊的植入 92632修正本
(implantation)之劑量與能量。熟悉此項技術者可基於電· 路之需要能採用最佳的源極/汲極的植入製程，而像這樣的 技術於此處並未揭露以免模糊本專利重點。除此之外，。 基於特殊電路之需要，在為了控制源極/汲極的接合 (junction)位置而進行源極/汲_極的離子植入之先，可任意 地形成侧壁間隔層（sidewal 1 spacer)(未圖示）。其後，可. 執行活化退火（activation annealing)處理俾以活化源極. /汲極220與230之區域。 [其他的實施例] · 如前所述，在CMP製程裡，可將研磨墊片（p〇lishing pad)附裝在平台（platen)表面以攪動正在研磨的研磨液。 研磨墊片可具有可影響平坦化之紋習慣性 地，研磨墊片（以下簡稱為墊片）可分類為，，硬，，墊片又稱之 為)型藝片，與，，軟，，塾片又稱之為β型塾片^型塾片特 別是用來作卜夬速平坦化而B型墊片一般更多是用來作均勻 的平坦化。
為了從單一的墊片完成高度平坦化與高度均勻性，可 開心種包含A型與B型特徵之塾片。第6A圖為這類塾片 之圖形。如其所示，墊片601包含多重薄片（nnmiple 1 (例如第6圖所tf有6個薄片）’它們之間是以a 溥片602與B型薄片603相互間隔排列。可使用此單一 墊片601同時提供有效的平坦化與均一性。 92632修正本 13 ^r6 ；,JT·- 保广 W卩開發出提供不同程度的平坦化與均勻性之 研磨墊片。例如，若名執H Rni、山 、/·玍之 右在墊“〇1裡中有四片是A型薄片另 ，A朽疋！缚片則此墊片之作用有67%為平坦化而37 4為均勻性之傾向。 f 6B圖為圖示研磨塾片在設計上的另—種實施例。塾 包3於第一墊片型態（例如A型）的内部區域61丨和 且一墊片型態（例如Bs)的外部環狀612。墊片6ι〇提供 具有其邊緣能均勻性控制的高速明坦化。此種功效是使用 傳統個別的塾片很困難達成的。 效疋使用 ^如先前的參照第3圖、第4A圖與第4B圖所作的討論， =閘極材料層320層沉積覆蓋鰭狀物21〇上時，位於覆蓋 鰭狀210上之中心將產生突出物（pr〇tnjsi〇n)。如上所= 的夕步驟CMP製程可平坦閘極材料層32〇而在閘極材料層 320上形成更均勻的表面。在一些實施例裡，於緊鄰著鰭 狀210額外地設置假的鰭狀結構（dummy fin s打uc忉『a) 俾以幫助平坦化製程而產生更均勻的閘極材料層32〇。 第7圖為說明假的鰭狀結構之横截面圖。第7圖一般 說來與第3圖所顯示出來的截面圖相似，除此之外，由第 7圖裡可看出緊鄰於真正的鰭狀21〇已經形成假的鰭狀物 701與假的鰭狀物702。假的鰭狀物701與702並不是扮演 在F i nFET的最後操作角色。然而在靠近於鰭狀21 〇的部位 設置鰭狀物701與702，當它們開始沉積時，將可使閘極 材料層3 2 0形成更均勻之分佈。也就是說，在閘極材料層 3 2 0裡叙的知狀7 01與7 0 2造成低點（1 ow p〇 i πt)於相鄰於 92632修正本 〜—_____
?(年4月夕:ftJ
* *- ‘―· —----I, ,J 鰭狀物210附近的區域比起若鰭狀物7〇1與7〇2不存在時 來的尚。因此，如第7圖所示之實施例中，閘極材料層32〇 在一開始就有比不具有假的鰭狀物7〇1與7〇2時更加均勻 性。這將導致在平坦化之後有較好的均勻性。 假的鰭狀物701與702可於埋藏氧化物層120上之各 種位置上以許多不同的形狀上能形成。例如，正方形、矩_ 形或圓圈形，或其他形狀，就像多角形，的圖案。假的鰭 狀物701與702得以。在許多FinFET的實施例中，氧化物 基底層（oxide-base layer)(例如，乙基烧氧化石夕（原石夕酸籲 乙酯）（tetraethyl〇rtho-silicate;TEOS))可用來作上述 之多晶矽之閘極層。而這些實施例亦可使用假的鰭狀物 701 與 702 。 在許多CMP的應用上，研磨TE〇s層至多晶矽層。第 8A圖說明一 TE0S層801沉積覆蓋在多晶矽結構8〇2上。 第8B圖表示當平坦TE0S層801至多晶矽結構802之層後， 其TE0S層801與多晶石夕結構的情形。可使用高選擇率的研籲 磨液（highly selective slurry)(例如選擇丰大於 6〇 : 1) 在這些平坦化製程裡。 然而，藉由添加介面活性劑和調整研磨液的酸鹼值，. 可調整氧化物（oxide)對多晶矽（p〇iysiiic〇n)的選擇率。 尤其，使用聚氧乙烯或聚氧丙烯嵌段共聚物醚類型 (ρ 1 uron 1 c)、陽離子與非離子型的介面活性劑能開發出更 有效的研磨液。 結論 92632修正本 在此處描述以多步騾的CMP製程而產生之 步驟的CMP製程提供有效的且具高度可控制性的FlnFET 之閛極多晶矽的平坦化。 在先前的描述中，提出許多特別的細節，諸如’特定 勺物貝’’·“冓、化學物質、製程·..等等，為的是供 徹f了解本發明之說明1而不需要求助於此說明的特定 1印也能貫施本發明。在其他的例子，像—些已知之製程 構，並未予以詳述，其理由是為了不要模糊本發明之要 用以製程根據本發明之半導體裝置的彳電層與導電層 可用傳統的沉積技術來沉積。例如，金屬化技術，就像各 種不同的化學氣相沉積（CVD)製程，包含低壓化學氣相沉積 (LCVD)與輔強化學氣相沉積（ECVD)均可使用。 本發明是適用在半導體裝置的製造，並且尤其是設計 特徵在lOOrnn或更小之半導體裝置而增加電晶體及電路之 速度和增進可靠度。本發明是適用在任何各式各樣的半導 體裝置，於此處並未詳盡地提出這些裝置之細節是因為要 避免模糊了本發明的發明要點。在實施本發明時，仍然利 用傳統的微影（photo 1 i thograph i C)與蝕刻技術，而於此處 未詳盡地描述這些技術是因為要避免模糊了本發明的發明 要點。 僅有本發明的這些較好的具體化實施例以及本發明所 揭露如上所述之一些變化例子。可了解到本發明是能夠用 在各式各樣其他的組合與狀況下並且於此處陳述的本發明 92632修正本 16 伊 3011 ψ>'-,ψ. 觀念内能夠改變。 【圖式簡單說明】 附圖中具有相同的元件符號表示遍佑 .;, 、邱於整個說明壹中 相似的元件。 < /3曰甲 第1圖表示半導體裝置之橫截面圖。 第2Α圖表示第1圖所示之半導體梦番 構之上視圖。 、置上形成鰭狀物結 第2Β圖表示第2Α圖中沿著α-α，線所得到的橫截面圖。 八弟3圖表示覆蓋在整個如第邡圖所示的鰭狀物之閘極 ;丨電層與閘極材料之橫截面圖。 第4Α圖表示根據與本發明一致的示範平坦化製程之 閘極材料的平坦化圖。 第4Β圖表示根據與本發明一致的示範平坦化製程之 間極材料之更進一步的平坦化圖。 第5圖疋概略表示從第3圖所示的閘極材料顯示其圖 案一閘極結構之F i nFET的上視圖。 第6A圖與第6B圖表示研磨墊片之圖形。 第7圖表示具有假鰭狀物之FinFET的橫裁面圖；而 第8A圖與苐圖表示沉積在多晶石夕層上之平坦化一 TE0S層的橫截面圖。 【主要元件符號說明】 1〇〇 鰭狀場效電晶體 100半導體裳置1H)矽基材 120埋藏氧化物層13〇矽層 17 92632修正本 K53011 140 介電蓋 140 介電層 150 光阻劑光罩 210 鰭狀物 220 源極範圍 230 汲極 310 犧牲氧化物膜 320 閘極材料層 320 閘極材料層 510 閘極結構 601 墊片 602Α 型薄片 603Α 型薄片 611 内部區域 612 外部環狀 701 假的鰭狀物 702 假的鰭狀物 801 TEOS 層 802 多晶矽結構 18 92632修正本

Claims (1)

  1. 州m 1 ί〇0^7月【| 第093116517號專利申請案 100年7月11日修正替換頁 十、申請專利範圍： •一種製造半導體裝置的方法，包括： 在絕緣層（120)上形成鰭狀結構（2〗〇), ^至少部分的該鰭狀結構⑽)與部分的該絕緣 層（120)上形成閘極結構（32〇), 使用第-研磨液以執行該閘極結構的化學機械 研磨（CMP)以進行該閘極結構之平坦化·以及 使用不同於該第一研磨液之第二研磨液以 該=極結構的化學機械研磨以進行該閘極結構（32〇) 之第一次平坦化’該閘極結構（32〇)之第二次平坦化 體裳置的通道區域裡之該鰭狀結構上之該 間極結構高度，而提高該鰭狀結構周圍之㈣極 之咼度。 2. ^申請專利範圍第1項之方法，μ，❹該第-研 =之該閉極結構(32〇)的化學機械研磨用以移除閉 極材料之速率比使用該第__ 化學機械㈣更快。 磨液之該閘極結構的 3. 請專利範圍第1項之方法，其中’在使用該第一 研磨液以執行該閘極結構的化學機械研磨以平班化 該閘極結構（32G)之後，在該閘極結構伸出5G〇h大 ^ 1500A於該半導體裝置的通道區域裡之該 構（210)上面。 ^申請專利範圍第3項之方法，其中，使用該第二研 1液以執行㈣極結構的化學機械研磨以平坦化該 /V極結構（320)之後’該閘極結構伸出大略3〇〇人於該 92632(修正本) 19 4. 1353011 第093116517號專利申請案 | 100年7月11曰修正替換頁 半導體裝置的通道區域裡之該鰭狀結構上面。 5. 如申睛專利挑圍第1項之方法，其中，該半導體裝置 為鰭狀場效電晶體（FinFET)。 6. 如申請專利範圍第1項之方法，其中，該第一研磨液 為具有酸驗值範圍大約從1 〇.5至11.5之二氧化石夕基 底的缓衝研磨液並且包含濃度範圍大約從01%至4 %的驗性成分。 7. 如申請專利範圍第1項之方法，其中，該第二研磨液 為具有酸鹼值範圍大約從10.5至11.5之二氧化石夕基 底的緩衝研磨液並且包含濃度範圍大約從〇.1%至1 %的鹼性成分。 8. —種形成金屬氧化物半導體場效電晶體（m〇sfET)裝 置之方法，包括： 在絕緣層（120)上形成源極（220)、汲極（230)與鰭 狀結構（210)，部分的該鰭狀結構（21〇)充當作為該 MOSFET的通道，以及形成介電層（31〇，14〇)於該鰭狀 結構之周圍； 沉積多晶矽層（320)於該鰭狀結構（210)之上，該 多晶矽層充當作為該MOSFET的閘極區域； 以第一速率平坦化該多晶矽層（320);以及 以比該第一速率更低的第二速率進一步平坦化 該多晶矽層（320) ’其中，該多晶矽層（32〇)之進一步 的平坦化降低位於該鰭狀結構上方之該多晶矽層的 高度’而提高在鄰近該鰭狀結構之區域之該多晶矽層 之高度。 20 92632(修正本) 1353011 9. 第093116517號專利申請案 100年7月11日修正替換頁 —I · 如申請專利範圍第8項之方法，其中，以該第一速率 . 與該第二速率來平坦化該多晶矽層（320)包含使用第 一研磨液與第二研磨液之該多晶矽層的化學機械研 磨（CMP)。
    21 92632(修正本)
    Lr· 七、指定代表圖： (一） 本案指定代表圖為：第（4A )圖。 (二） 本代表圖之元件符號簡單說明： 100 籍狀場效電晶爱 £ 100 半導體裝置 110 石夕基材 120 埋藏氧化物層 130 矽層 210 鰭狀物 310 犧牲氧化物膜 320 閘極材料層 320 間極材料層 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式： 4 92632修正本
TW093116517A 2003-06-12 2004-06-09 Multi-step chemical mechanical polishing of a gate TWI353011B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/459,495 US6855607B2 (en) 2003-06-12 2003-06-12 Multi-step chemical mechanical polishing of a gate area in a FinFET

Publications (2)

Publication Number Publication Date
TW200520081A TW200520081A (en) 2005-06-16
TWI353011B true TWI353011B (en) 2011-11-21

Family

ID=33510825

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093116517A TWI353011B (en) 2003-06-12 2004-06-09 Multi-step chemical mechanical polishing of a gate

Country Status (8)

Country Link
US (2) US6855607B2 (zh)
JP (1) JP2007500456A (zh)
KR (1) KR101062986B1 (zh)
CN (1) CN1806318B (zh)
DE (1) DE112004001041B4 (zh)
GB (1) GB2419232B (zh)
TW (1) TWI353011B (zh)
WO (1) WO2004112105A2 (zh)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6855607B2 (en) * 2003-06-12 2005-02-15 Advanced Micro Devices, Inc. Multi-step chemical mechanical polishing of a gate area in a FinFET
US20040266115A1 (en) * 2003-06-25 2004-12-30 Bor-Wen Chan Method of making a gate electrode on a semiconductor device
GB2403810B (en) * 2003-07-10 2005-06-08 Schlumberger Holdings Method and apparatus for imaging earth formation
KR100487567B1 (ko) * 2003-07-24 2005-05-03 삼성전자주식회사 핀 전계효과 트랜지스터 형성 방법
US7087471B2 (en) * 2004-03-15 2006-08-08 International Business Machines Corporation Locally thinned fins
KR100605104B1 (ko) * 2004-05-04 2006-07-26 삼성전자주식회사 핀-펫 소자 및 그 제조 방법
US7388257B2 (en) * 2004-09-01 2008-06-17 International Business Machines Corporation Multi-gate device with high k dielectric for channel top surface
US7446046B2 (en) * 2005-01-06 2008-11-04 Intel Corporation Selective polish for fabricating electronic devices
KR100666368B1 (ko) * 2005-08-09 2007-01-09 삼성전자주식회사 트랜지스터 및 그 제조 방법
KR100655379B1 (ko) * 2005-11-25 2006-12-08 삼성전자주식회사 유효 출력 데이터 윈도우를 확장시킬 수 있는 출력회로,이를 구비한 반도체 메모리 장치, 및 유효 출력 데이터확장방법
ATE544178T1 (de) * 2006-07-11 2012-02-15 Nxp Bv Halbleiterbauelemente und verfahren zur herstellung
DE102006035667B4 (de) * 2006-07-31 2010-10-21 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Verbessern der Lithographieeigenschaften während der Gateherstellung in Halbleitern mit einer ausgeprägten Oberflächentopographie
US7781312B2 (en) * 2006-12-13 2010-08-24 General Electric Company Silicon carbide devices and method of making
KR100829616B1 (ko) * 2006-12-27 2008-05-14 삼성전자주식회사 채널 실리콘막 형성 방법 및 이를 이용한 스택형 반도체소자 제조 방법
WO2009110048A1 (ja) * 2008-02-15 2009-09-11 日本ユニサンティスエレクトロニクス株式会社 半導体装置及びその製造方法
CN102117737B (zh) * 2009-12-30 2015-01-07 中国科学院微电子研究所 减小半导体器件中ler的方法及半导体器件
US8497210B2 (en) * 2010-10-04 2013-07-30 International Business Machines Corporation Shallow trench isolation chemical mechanical planarization
US9385050B2 (en) * 2011-01-06 2016-07-05 Globalfoundries Inc. Structure and method to fabricate resistor on finFET processes
US8361854B2 (en) 2011-03-21 2013-01-29 United Microelectronics Corp. Fin field-effect transistor structure and manufacturing process thereof
US8466502B2 (en) 2011-03-24 2013-06-18 United Microelectronics Corp. Metal-gate CMOS device
US8710596B2 (en) 2011-05-13 2014-04-29 United Microelectronics Corp. Semiconductor device
US8853013B2 (en) 2011-08-19 2014-10-07 United Microelectronics Corp. Method for fabricating field effect transistor with fin structure
US8647986B2 (en) * 2011-08-30 2014-02-11 United Microelectronics Corp. Semiconductor process
US8477006B2 (en) 2011-08-30 2013-07-02 United Microelectronics Corp. Resistor and manufacturing method thereof
US8507350B2 (en) 2011-09-21 2013-08-13 United Microelectronics Corporation Fabricating method of semiconductor elements
US8497198B2 (en) * 2011-09-23 2013-07-30 United Microelectronics Corp. Semiconductor process
US8946829B2 (en) * 2011-10-14 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications
US8722501B2 (en) 2011-10-18 2014-05-13 United Microelectronics Corp. Method for manufacturing multi-gate transistor device
US8871575B2 (en) 2011-10-31 2014-10-28 United Microelectronics Corp. Method of fabricating field effect transistor with fin structure
US9006092B2 (en) 2011-11-03 2015-04-14 United Microelectronics Corp. Semiconductor structure having fluoride metal layer and process thereof
US8975672B2 (en) 2011-11-09 2015-03-10 United Microelectronics Corp. Metal oxide semiconductor transistor and manufacturing method thereof
US8921206B2 (en) 2011-11-30 2014-12-30 United Microelectronics Corp. Semiconductor process
US9698229B2 (en) 2012-01-17 2017-07-04 United Microelectronics Corp. Semiconductor structure and process thereof
US8987096B2 (en) 2012-02-07 2015-03-24 United Microelectronics Corp. Semiconductor process
US8536072B2 (en) 2012-02-07 2013-09-17 United Microelectronics Corp. Semiconductor process
US9006107B2 (en) 2012-03-11 2015-04-14 United Microelectronics Corp. Patterned structure of semiconductor device and fabricating method thereof
US9142649B2 (en) 2012-04-23 2015-09-22 United Microelectronics Corp. Semiconductor structure with metal gate and method of fabricating the same
US11037923B2 (en) * 2012-06-29 2021-06-15 Intel Corporation Through gate fin isolation
US8501636B1 (en) 2012-07-24 2013-08-06 United Microelectronics Corp. Method for fabricating silicon dioxide layer
US9064931B2 (en) 2012-10-11 2015-06-23 United Microelectronics Corp. Semiconductor structure having contact plug and metal gate transistor and method of making the same
US8927388B2 (en) 2012-11-15 2015-01-06 United Microelectronics Corp. Method of fabricating dielectric layer and shallow trench isolation
US8883621B2 (en) 2012-12-27 2014-11-11 United Microelectronics Corp. Semiconductor structure and method of fabricating MOS device
KR102003276B1 (ko) 2013-02-14 2019-07-24 삼성전자 주식회사 반도체 소자 제조 방법
US9076870B2 (en) 2013-02-21 2015-07-07 United Microelectronics Corp. Method for forming fin-shaped structure
US9196352B2 (en) 2013-02-25 2015-11-24 United Microelectronics Corp. Static random access memory unit cell structure and static random access memory unit cell layout structure
US8753902B1 (en) 2013-03-13 2014-06-17 United Microelectronics Corp. Method of controlling etching process for forming epitaxial structure
CN104051248B (zh) * 2013-03-13 2017-03-22 中芯国际集成电路制造(上海)有限公司 栅极的形成方法
US9214395B2 (en) 2013-03-13 2015-12-15 United Microelectronics Corp. Method of manufacturing semiconductor devices
US9093285B2 (en) 2013-03-22 2015-07-28 United Microelectronics Corp. Semiconductor structure and process thereof
US9147747B2 (en) 2013-05-02 2015-09-29 United Microelectronics Corp. Semiconductor structure with hard mask disposed on the gate structure
US9230812B2 (en) 2013-05-22 2016-01-05 United Microelectronics Corp. Method for forming semiconductor structure having opening
US9349812B2 (en) 2013-05-27 2016-05-24 United Microelectronics Corp. Semiconductor device with self-aligned contact and method of manufacturing the same
US8993433B2 (en) 2013-05-27 2015-03-31 United Microelectronics Corp. Manufacturing method for forming a self aligned contact
US9064814B2 (en) 2013-06-19 2015-06-23 United Microelectronics Corp. Semiconductor structure having metal gate and manufacturing method thereof
CN104282564B (zh) * 2013-07-03 2018-12-21 中芯国际集成电路制造(上海)有限公司 半导体器件和鳍式场效应晶体管的形成方法
US9406682B2 (en) 2014-09-12 2016-08-02 International Business Machines Corporation Method and structure for preventing epi merging in embedded dynamic random access memory
JP6858763B2 (ja) * 2015-09-30 2021-04-14 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 多結晶仕上げを有する半導体ウエハを処理する方法
KR102434914B1 (ko) 2016-01-15 2022-08-23 삼성전자주식회사 반도체 소자의 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
US10541139B2 (en) * 2016-03-24 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Planarization control in semiconductor manufacturing process
US11031250B2 (en) 2018-11-29 2021-06-08 International Business Machines Corporation Semiconductor structures of more uniform thickness

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW358983B (en) * 1997-11-15 1999-05-21 Taiwan Semiconductor Mfg Co Ltd Chemical mechanical grinding method
US6162368A (en) * 1998-06-13 2000-12-19 Applied Materials, Inc. Technique for chemical mechanical polishing silicon
KR100502676B1 (ko) * 1998-09-16 2005-10-14 주식회사 하이닉스반도체 반도체 소자의 제조 방법
JP3099002B1 (ja) * 1999-06-25 2000-10-16 茂徳科技股▲ふん▼有限公司 ２段階化学機械研磨方法
KR100533167B1 (ko) * 1999-09-10 2005-12-02 주식회사 하이닉스반도체 반도체 소자 및 그의 제조 방법
US6431959B1 (en) * 1999-12-20 2002-08-13 Lam Research Corporation System and method of defect optimization for chemical mechanical planarization of polysilicon
JP2001319900A (ja) * 2000-05-10 2001-11-16 Toshiba Ceramics Co Ltd 半導体基板の研磨方法
KR100592769B1 (ko) * 2000-12-20 2006-06-26 매그나칩 반도체 유한회사 반도체 디바이스의 트랜지스터 및 그 제조 방법
JP2002231662A (ja) * 2001-01-22 2002-08-16 Promos Technol Inc 化学機械平坦化方法
US6531410B2 (en) * 2001-02-27 2003-03-11 International Business Machines Corporation Intrinsic dual gate oxide MOSFET using a damascene gate process
US6458662B1 (en) * 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
US6855607B2 (en) * 2003-06-12 2005-02-15 Advanced Micro Devices, Inc. Multi-step chemical mechanical polishing of a gate area in a FinFET
US7095065B2 (en) * 2003-08-05 2006-08-22 Advanced Micro Devices, Inc. Varying carrier mobility in semiconductor devices to achieve overall design goals

Also Published As

Publication number Publication date
US20050118824A1 (en) 2005-06-02
KR101062986B1 (ko) 2011-09-07
US20040253775A1 (en) 2004-12-16
TW200520081A (en) 2005-06-16
US6855607B2 (en) 2005-02-15
KR20060020674A (ko) 2006-03-06
WO2004112105A2 (en) 2004-12-23
US7125776B2 (en) 2006-10-24
DE112004001041B4 (de) 2010-04-29
DE112004001041T5 (de) 2006-04-20
GB0526386D0 (en) 2006-02-08
CN1806318B (zh) 2010-05-12
WO2004112105A3 (en) 2005-02-24
JP2007500456A (ja) 2007-01-11
CN1806318A (zh) 2006-07-19
GB2419232B (en) 2007-01-17
GB2419232A (en) 2006-04-19

Similar Documents

Publication Publication Date Title
TWI353011B (en) Multi-step chemical mechanical polishing of a gate
US10256302B2 (en) Vertical transistor with air-gap spacer
KR100874960B1 (ko) 고 이동도 반도체 어셈블리, 고 이동도 반도체 기판 및 고이동도 반도체 어셈블리의 제조 방법
TWI338328B (en) Dual silicon layer for chemical mechanical polishing planarization
US6872647B1 (en) Method for forming multiple fins in a semiconductor device
US7534686B2 (en) Multi-structured Si-fin and method of manufacture
TWI411107B (zh) 高效能金氧半場效電晶體
US20050272190A1 (en) Methods of fabricating fin field-effect transistors having silicide gate electrodes and related devices
US7892911B2 (en) Metal gate electrodes for replacement gate integration scheme
TWI313932B (en) Semiconductor device with increased channel area and decreased leakage current
US20080296681A1 (en) Contact structure for finfet device
TWI377596B (en) Method and apparatus to increase strain effect in a transistor channel
US20170222055A1 (en) Semiconductor device and manufacturing method thereof
TWI505349B (zh) 製造半導體裝置之方法
TW200425425A (en) Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
CN108987345B (zh) 具有双浅沟槽隔离及可调内外鳍片轮廓的鳍片制程
US11295988B2 (en) Semiconductor FET device with bottom isolation and high-κ first
TW201832274A (zh) 半導體裝置的製造方法
CN110034015A (zh) 一种纳米线围栅器件的形成方法
US7041542B2 (en) Damascene tri-gate FinFET
US10269944B2 (en) Fin semiconductor device and method of manufacture with source/drain regions having opposite conductivities
GB2488634A (en) Semiconductor device structure and manufacturing method thereof
US10147648B1 (en) Vertical fin gate structure for RF device
TWI713115B (zh) 平坦化方法以及製造半導體結構的方法
US7091068B1 (en) Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees