DE10104780A1 - Verfahren zur Herstellung eines Steckkontakts in einem Halbleiterbauelement - Google Patents
Verfahren zur Herstellung eines Steckkontakts in einem HalbleiterbauelementInfo
- Publication number
- DE10104780A1 DE10104780A1 DE10104780A DE10104780A DE10104780A1 DE 10104780 A1 DE10104780 A1 DE 10104780A1 DE 10104780 A DE10104780 A DE 10104780A DE 10104780 A DE10104780 A DE 10104780A DE 10104780 A1 DE10104780 A1 DE 10104780A1
- Authority
- DE
- Germany
- Prior art keywords
- plug contact
- producing
- seg
- semiconductor component
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- 238000011065 in-situ storage Methods 0.000 abstract description 4
- 230000001771 impaired effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 15
- 239000003990 capacitor Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims (7)
Aufwachsen eines SEG-Steckkontakts auf ein Halbleitersubstrat, in dem verschiedene Komponenten zur Bildung eines Halbleiterbauelements ausgebildet sind, mittels des selektiven Aufwachsverfahrens;
thermisches Dotieren mit Fremdatomen während des Aufwachsens des SEG-Steckkontakts; und
thermisches Dotieren mit Fremdatomen nach dem Aufwachsen des SEG-Steckkontakts.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2000-35680 | 2000-06-27 | ||
KR10-2000-0035680A KR100407683B1 (ko) | 2000-06-27 | 2000-06-27 | 반도체 소자의 콘택 플러그 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10104780A1 true DE10104780A1 (de) | 2002-01-31 |
DE10104780B4 DE10104780B4 (de) | 2009-07-23 |
Family
ID=19674201
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10104780A Expired - Fee Related DE10104780B4 (de) | 2000-06-27 | 2001-02-02 | Verfahren zur Herstellung eines Steckkontakts in einem Halbleiterbauelement |
Country Status (4)
Country | Link |
---|---|
US (1) | US6399488B2 (de) |
JP (1) | JP4583646B2 (de) |
KR (1) | KR100407683B1 (de) |
DE (1) | DE10104780B4 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010035857A (ko) * | 1999-10-04 | 2001-05-07 | 윤종용 | 반도체소자 및 그 제조방법 |
KR100596834B1 (ko) * | 2003-12-24 | 2006-07-04 | 주식회사 하이닉스반도체 | 반도체소자의 폴리실리콘 플러그 형성방법 |
US20080286967A1 (en) * | 2007-05-18 | 2008-11-20 | Atmel Corporation | Method for fabricating a body to substrate contact or topside substrate contact in silicon-on-insulator devices |
US8815735B2 (en) | 2012-05-03 | 2014-08-26 | Nanya Technology Corporation | Semiconductor device and method of manufacturing the same |
KR20160018221A (ko) * | 2014-08-08 | 2016-02-17 | 에스케이하이닉스 주식회사 | 3차원 반도체 집적 회로 장치 및 그 제조방법 |
KR102240024B1 (ko) | 2014-08-22 | 2021-04-15 | 삼성전자주식회사 | 반도체 장치, 반도체 장치의 제조방법 및 에피택시얼층의 형성방법 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6115372A (ja) * | 1984-07-02 | 1986-01-23 | Toshiba Corp | 半導体装置およびその製造方法 |
JPS6298747A (ja) * | 1985-10-25 | 1987-05-08 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH0682628B2 (ja) * | 1985-11-07 | 1994-10-19 | 松下電子工業株式会社 | 半導体装置の製造方法 |
JPH0812918B2 (ja) * | 1986-03-28 | 1996-02-07 | 株式会社東芝 | 半導体装置の製造方法 |
JPH01205525A (ja) * | 1988-02-12 | 1989-08-17 | Sony Corp | コンタクトホールの穴埋め方法 |
US5378652A (en) * | 1989-04-19 | 1995-01-03 | Kabushiki Kaisha Toshiba | Method of making a through hole in multi-layer insulating films |
JPH0497519A (ja) * | 1990-08-15 | 1992-03-30 | Nec Corp | 半導体装置の製造方法 |
US5134454A (en) * | 1990-09-26 | 1992-07-28 | Purdue Research Foundation | Self-aligned integrated circuit bipolar transistor having monocrystalline contacts |
JPH04163914A (ja) * | 1990-10-29 | 1992-06-09 | Nec Corp | 半導体装置の製造方法 |
JPH05217916A (ja) * | 1992-01-31 | 1993-08-27 | Nec Corp | 半導体装置の製造方法 |
JP3156878B2 (ja) * | 1992-04-30 | 2001-04-16 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP3761918B2 (ja) * | 1994-09-13 | 2006-03-29 | 株式会社東芝 | 半導体装置の製造方法 |
SE508635C2 (sv) * | 1995-11-20 | 1998-10-26 | Ericsson Telefon Ab L M | Förfarande för selektiv etsning vid tillverkning av en bipolär transistor med självregistrerande bas-emitterstruktur |
US5753555A (en) * | 1995-11-22 | 1998-05-19 | Nec Corporation | Method for forming semiconductor device |
JP2877108B2 (ja) * | 1996-12-04 | 1999-03-31 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JP2000156502A (ja) * | 1998-09-21 | 2000-06-06 | Texas Instr Inc <Ti> | 集積回路及び方法 |
-
2000
- 2000-06-27 KR KR10-2000-0035680A patent/KR100407683B1/ko not_active IP Right Cessation
-
2001
- 2001-02-02 DE DE10104780A patent/DE10104780B4/de not_active Expired - Fee Related
- 2001-03-23 JP JP2001084530A patent/JP4583646B2/ja not_active Expired - Fee Related
- 2001-06-12 US US09/879,555 patent/US6399488B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR100407683B1 (ko) | 2003-12-01 |
US6399488B2 (en) | 2002-06-04 |
US20020009882A1 (en) | 2002-01-24 |
KR20020001246A (ko) | 2002-01-09 |
JP2002025936A (ja) | 2002-01-25 |
DE10104780B4 (de) | 2009-07-23 |
JP4583646B2 (ja) | 2010-11-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8101 | Request for examination as to novelty | ||
8105 | Search report available | ||
8110 | Request for examination paragraph 44 | ||
8128 | New person/name/address of the agent |
Representative=s name: HOEFER & PARTNER, 81543 MUENCHEN |
|
8364 | No opposition during term of opposition | ||
R081 | Change of applicant/patentee |
Owner name: INTELLECTUAL DISCOVERY CO., LTD., KR Free format text: FORMER OWNER: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., ICHON, KYONGGI, KR Effective date: 20140220 Owner name: INTELLECTUAL DISCOVERY CO., LTD., KR Free format text: FORMER OWNER: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., ICHON, KR Effective date: 20140220 |
|
R082 | Change of representative |
Representative=s name: HOEFER & PARTNER PATENTANWAELTE MBB, DE Effective date: 20140220 Representative=s name: HOEFER & PARTNER, DE Effective date: 20140220 |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |