CN1976059A - 鳍片型场效应晶体管结构以及用于制造这种结构的方法 - Google Patents
鳍片型场效应晶体管结构以及用于制造这种结构的方法 Download PDFInfo
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
一种包括位于衬底上面的半导体鳍片的半导体结构以及它的制造方法。栅电极位于所述半导体鳍片的上面。该栅电极在位于离半导体鳍片较近处的第一区域中具有第一应力,并且在位于离半导体鳍片较远处的第二区域中具有不同于第一应力的第二应力。所述半导体鳍片还可在衬底内部的基座上面对齐。在适当的应力条件下对所述半导体结构进行退火,以获得半导体器件性能的增强。
Description
技术领域
本发明一般涉及半导体结构。尤其是,本发明涉及通过在半导体结构内部利用机械应力效应和/或掺杂物再分布效应来增强半导体器件的性能。
背景技术
由于半导体技术的进步和半导体器件密度需求的增加,增加了对制造具有减小的尺寸比如较小器件栅电极长度的半导体器件(例如金属氧化物半导体场效应晶体管(MOSFET)器件)的需求。一种适应由于尺寸的显著减小而增大的密度的新颖半导体结构是使用了鳍片型场效应晶体管(finFET)结构的双栅器件。finFET结构提供了一条垂直沟道器件,其包括一条在衬底上侧向设置的半导体鳍片。为了获得理想的短沟道效应(SCE)控制,半导体鳍片在器件沟道区域中足够细,以确保形成完全耗尽的半导体器件。一般,一对栅介电层位于一对相对的半导体鳍片侧壁上。一般,一个呈倒置U形的栅电极位于半导体鳍片上并覆盖住所述那对栅介电层。在某些其它情况下,栅电极并非位于所述鳍片的顶上,因此会受到所述鳍片侧壁的限制。
除了提供具有理想的SCE控制的空间效率高的晶体管结构的finFET结构之外,半导体器件现在通常被设计成使用机械应力效应(MSE)和/或掺杂物再分布或迁移效应来增强晶体管的性能。MSE通常被用来在半导体器件内部提供增强的电荷载流子迁移率。一般,增强的电荷载流子迁移率会带来增强的半导体器件性能。
finFET结构可用受应力的组件制造以提高finFET结构的性能。例如:(1)Rim在美国专利No.6815738中和(2)Lee等人在专利公开No.2004/0256647中均提出了finFET内部的受应力的半导体鳍片结构。当形成受应力的半导体鳍片结构时,他们均通过利用分层组件的点阵错位来形成所述受应力的半导体鳍片结构。
由于在半导体器件技术中,理想的SCE控制和finFET器件的空间效率高的优点可能一直被认为相当重要,并且由于受应力的结构同样也一直用于提供具有增强性能的半导体器件,所以可能会继续在finFET内部使用受应力的结构。
发明内容
本发明提供了一对finFET结构和一种用于制造finFET结构的方法。
这对finFET结构中的第一个结构包括位于衬底上面的半导体鳍片。该结构还包括位于半导体鳍片上面的栅电极。在该第一个结构之中,栅电极在位于离半导体鳍片较近处的第一区域中具有第一应力,并且在位于离半导体鳍片较远处的第二区域中具有不同于第一应力的第二应力。
这对finFET结构中的第二个结构包括位于衬底内部的基座上面的半导体鳍片。最好,该半导体鳍片在衬底内部的基座上面对齐设置。
所述方法从所述finFET结构中的第一个结构开始。这种方法包括在衬底上面形成半导体鳍片。该方法还包括在半导体鳍片上形成一个栅电极,其中所述栅电极在位于离半导体鳍片较近处的第一区域中具有第一应力,并且在位于离半导体鳍片较远处的第二区域中具有不同于第一应力的第二应力。
附图说明
正如下面描述的那样,本发明的目的、特征以及优点参考具体实施方式得以理解。优选实施方式参考附图得以理解,附图构成了本公开的实体部分,其中:
图1至图13显示了一系列的示意性截面图和平面视图,示出了在制造根据本发明的优选实施例的finFET结构的过程中逐个阶段的结果。
具体实施方式
本发明提供了一种具有增强的性能的finFET结构、和一种用于制造这种finFET结构的方法。
图1至图13显示了一系列的示意性截面图和平面视图,示出了在制造根据本发明的优选实施例的finFET结构的过程中逐个阶段的结果。
具体来说,图1显示了具有埋入介电层12的衬底10,埋入介电层12位于衬底10之上。半导体层14位于埋入介电层12之上。硬掩模层16位于半导体层14之上。最后,图案化光致抗蚀层18位于硬掩模层16之上。
衬底10可包含几种材料中的任意一种,这些材料包括但不仅限于:导体材料、半导体材料或介电材料。一般,衬底10包含半导体材料。半导体材料可从包括但不仅限于下述物质中的组中选取:硅(Si)、锗(Ge)、硅锗(SiGe)合金、碳化硅(SiC)、碳化硅锗合金(SiGeC)和诸如(III-VI)和(II-VI)半导体材料这样的化合物半导体材料。化合物半导体材料的非限制性例子包括砷化镓、砷化铟和磷化铟材料。一般,衬底10具有从大约1到大约3密耳的厚度。
当衬底10包含有半导体材料时,埋入介电层12通常包含构成衬底10的半导体材料的氧化物。可选择地,埋入介电层12可包含氮化物、氮氧化物或其它介电材料。埋入介电层12可以利用半导体制造技术领域的常规方法形成。这些方法的非限制性例子包括热退火方法、化学气相淀积法和物理气相淀积法。一般,埋入介电层12具有从大约200到大约10000埃的厚度。
半导体层14可包含几种半导体材料中的任何一种,这些材料也是本技术领域中的常规材料。半导体材料可包括,但不仅限于:硅、锗、硅锗合金、碳化硅、碳化硅锗合金、砷化镓(GaAs)、砷化铟(InAs)、磷化铟(InP)、以及其它化合物(III-V)和(II-VI)半导体材料。半导体层14也可包含有机半导体材料。一般,半导体层14具有从大约300到大约1000埃的厚度。
衬底10(当包含半导体材料时)、埋入介电层12和半导体层14共同构成绝缘体上半导体衬底。在本发明的实施例中,衬底10一般包含硅或硅锗合金半导体材料,埋入介电层12一般包含相应的硅或硅锗的氧化物材料,并且半导体层14也一般包含相应的硅或硅锗合金半导体材料。该绝缘体上半导体衬底可用半导体制造技术领域中的几种常规方法中的任何一种形成。这些方法的非限制性例子包括层转移方法、层压方法,尤其是注氧分离方法(SIMOX)。
硬掩模层16包含有硬掩模材料,这种材料也是本技术领域中的常规材料。硬掩模材料的非限制性例子一般包括硅和/或锗的氧化物、氮化物和氮氧化合物,但也可使用其它元素的氧化物、氮化物和氮氧化合物。前述的硬掩模材料可用以下方法淀积,所述方法包括但不仅限于:热退火方法、化学气相淀积法和物理气相淀积溅射方法。一般,硬掩模层16具有从大约200到400埃的厚度,尽管这个厚度并不会对该实施例或本发明造成限制。
图案化光致抗蚀剂层18可包含本技术领域中的常规光致抗蚀材料。非限制性例子包括阳性的光致抗蚀材料、阴性的光致抗蚀材料以及混合光致抗蚀材料。抗蚀剂可以被处理成利用本技术领域中常规的旋涂、曝光和显影方法和材料来形成图案化光致抗蚀剂层18。一般,图案化光致抗蚀剂层18具有从大约5000到大约15000埃的厚度。
图2显示了依次刻蚀硬掩模层16、半导体层14和部分埋入介电层12的结果,以产生相应的图案化硬掩模层16a,该图案化硬掩模层16a对齐设置在半导体鳍片14a上,而半导体鳍片14a对齐设置在刻蚀后的埋入介电层12′内部的基座13上。一般,基座13在刻蚀后的埋入介电层12′中具有大约200到大约400埃的高度。使用图案化光致抗蚀剂层18作为刻蚀掩模,来至少对硬掩模层16进行前述蚀刻来形成图案化硬掩模层16a。当从半导体层14形成半导体鳍片14a的图案时,以及一般还有当对埋入介电层12进行蚀刻来形成刻蚀后的埋入介电层12′时,利用带或不带图案化光致抗蚀剂层18a的图案化硬掩模层16a。
前述层最好被各向异性地刻蚀,以便由此提供基本上直的侧壁。一般,这种刻蚀利用活性离子刻蚀等离子刻蚀剂或其它的各向异性刻蚀剂,比如离子束刻蚀剂。尽管一般不太常用,但是在一定条件下也可使用湿式化学刻蚀剂材料,尽管它们一般是各向同性的刻蚀剂。当使用活性离子刻蚀等离子刻蚀剂时,在刻蚀含硬掩模材料的硅或含介电材料的硅时一般利用含氟的刻蚀剂气体成分。当刻蚀含有半导体材料的硅或锗时一般利用含氯的刻蚀剂气体成分。
图3显示了一对位于半导体鳍片14a的一对相对侧壁之上的栅介电层20。这对栅介电层20一般包含构成半导体鳍片14a的半导体材料的热氧化物。当使用加热技术时,栅介电层20如图所示形成于半导体鳍片14a的表面部分之内。可选择地,也可使用淀积的介电材料而不是热生长的介电材料。当使用淀积的电介质时,栅电介质将通常出现在半导体鳍片14a的侧壁上面和顶部之上。这种可供选择的淀积介电材料可包括,但不仅限于:其它的硅的氧化物、氮化物和氮氧化物,其一般具有在真空中测量的从大约4到大约20的介电常数;以及重金属氧化物,如氧化铪、硅酸铪、氧化铝、氧化钛、氧化镧、钛酸锶钡(BST)、锆钛酸铅(PZT)和其它的铁电体材料。重金属氧化物一般具有大于20,而且有可能高达至少100的电介质常数。一般,当由热氧化硅材料制成时,这对栅介电层20中的每一个具有从大约10到大约20埃的厚度。
图4显示的是位于半导体鳍片14a之上和刻蚀后的埋入介电层12′、栅介电层对20以及图案化硬掩模层16a上面的倒置U形栅电极22。一般,栅电极22包含有掺杂的聚硅材料(即,掺杂剂浓度为每立方厘米大约le18到le20个掺杂剂原子)。
可以利用可供选择的栅电极导体材料,只要它们是在名义上的晶态或有序态,其中有序态是指对去晶或非晶化或其它用以提供深度特定的非晶区或非结晶区域的处理敏感。这些其它导体材料因此包括,但不仅限于:某些金属、金属合金、金属氮化物和金属硅化物。栅电极22可使用在本技术领域常规的淀积和图案化方法形成。非限制性例子包括化学气相淀积法和物理气相淀积法。一般,栅电极22具有从大约800到大约1500埃的厚度。
图5显示了对应于图4中所示半导体结构的半导体结构的示意性平面视图。
图5显示了刻蚀后的埋入介电层12′。呈狗骨头形状的图案化硬掩模层16a位于刻蚀后的埋入介电层12′之上。半导体鳍片14a和一对栅介电层20在图案化硬掩模层16a的下面对齐。构件14a和20都没有在图5中具体示出。栅电极22横跨半导体鳍片14a和上覆的图案化硬掩模层16a中间部位。半导体鳍片14a上被栅电极22覆盖的部分包括沟道区域。半导体鳍片14a上没有被栅电极22覆盖的端部包括这样一个区域,其中可以依次设置和形成一对源极/漏极区域。图案化硬掩模层16a和在其下面对齐的半导体鳍片14a两者的狗骨头形状的目的都在于具有中心轴向部分,其延伸到一对线宽大于该中心轴向部分的突出(lobed)端部。中心轴向部分可具有从大约0.05到大约0.30微米的线宽,尽管该实施例和本发明都不局限于这个线宽范围。图5示出了图案化硬掩模层16a的突出端部为具有显著角形的狗骨头形状,但在如图5中示出的分立的finFET结构中,突出端部可选择地具有较少的角形特征。
类似地,尽管图5中的示意性平面视图示出了根据当前实施例的finFET为具有单个半导体鳍片和栅电极的分立器件,但是这种特殊结构并非对实施例或本发明加以限制。相反地,也可以想到这样的实施例,其中多个finFET器件可在一个方向上或在两个方向上都利用单个细长跨越栅电极(比如栅电极22)连接起来。多个器件也可在一个方向上或两个方向上都通过其它跨越半导体鳍片(比如半导体鳍片14a)连接起来。
图6显示了根据图5中所示的参考剖面6-6贯穿半导体鳍片14a的源极/漏极扩展区域的示意性截面图。
图6显示了位于刻蚀后的埋入介电层12′内部的基座13之上的半导体鳍片14a。图6也显示了位于半导体鳍片14a的相对侧壁之上的那一对栅介电层20和位于半导体鳍片14a顶上的图案化硬掩模层16a。最后,图6显示了一定剂量的初始注入离子21,其用于形成扩展注入和/或位于扩展区域内部的晕环式(halo)注入。一般,这一剂量的初始注入离子21相对于刻蚀后的埋入介电层12′的主平面具有从大约30°到大约45°的倾斜角度,并且处于finFET制造技术领域中常规的浓度。这一剂量的初始注入离子21还具有适合于所要制造的finFET的极性。
图7显示了一个示意性截面图,示出了对具有图6中所示示意性截面图的finFET进一步处理的结果。
图7显示了邻接型分隔层16′,其覆盖了所述一对栅介电层20的侧壁并合并了如图6中所示的图案化硬掩模层16a。一般,邻接型分隔层16′包含与构成图案化硬掩模层16a的硬掩模材料类似、相同或等同的分隔材料。典型的非限制性的材料包括氧化物、氮化物和氮氧化物。一般,邻接型分隔层16′是利用覆盖层(即,厚度从大约300到大约500埃)淀积步骤及随后的各向异性内刻蚀步骤形成的。化学气相淀积法(热激活和等离子体激活)和物理气相淀积法也可被用于覆盖层淀积。并不排除其它方法。
如图7所示的邻接型分隔层16′阻止了随着对具有图4所示示意性截面图的半导体结构进行进一步的非晶化离子注入处理而对在半导体鳍片层14a内部的源极/漏极以及扩展区域造成所不期望的离子注入损伤。因而,根据该实施例和本发明,图6中所示的扩展和晕环式离子注入处理以及图7中所示的邻接型分隔层处理一般都在对图4中所示半导体结构的附加非晶化离子注入处理之前进行。
图8显示了从图5中所示的参考剖面4-4看到的对图4所示半导体结构的这种附加的非晶化离子注入处理的结果。同样,附加的非晶化离子注入处理一般在图6和图7所示的处理之后进行。
图8显示了离子注入栅电极22以形成局部非晶化栅电极22′的结果。局部非晶化栅电极22′包含位于半导体鳍片14a附近的未非晶化子层22a(unamorphized sub-layer)。局部非晶化栅电极22′还包含非晶化子层22b作为表面层,该表面层位于离半导体鳍片14a较远处。局部非晶化栅电极22′被非晶化至与非晶化子层22b的厚度对应的距离。这个距离最好比半导体鳍片14a与刻蚀后的埋入介电层12′的交界面深。利用一定剂量的非晶化离子23进行非晶化作用。在非晶化离子也可被用来掺杂如图8所示半导体鳍片14a内部的源极/漏极区域中没有被局部非晶化栅电极22′覆盖的特定部分、或如图7所示的邻接型分隔层16′的较厚部分的情况下,这一剂量的非晶化离子23最好是还包含掺杂离子的一种非晶化离子。类似地,非晶化离子23也可包括不掺杂非晶化离子,比如锗的非晶化离子。也可以使用其它更重的不非晶化离子。一般,非晶化离子23(包括掺杂和不掺杂非晶化离子)的总体浓度为每立方厘米大约le18到大约le22个掺杂原子。非晶化离子23最好以如图6中所示的从大约30°到大约45°的倾斜角度提供,尽管这一点在当前的实施例或本发明中都不要求。
图9显示了位于局部非晶化栅电极22′之上的衬垫介电层24(paddielectric layer)、和位于衬垫介电层24之上的应力传递层26。
一般,衬垫介电层24包含用作衬垫介电层的常规材料的几种介电材料中的任何一种。非限制性例子包括氧化硅、氮化硅和氮氧化硅材料。氧化硅材料特别常用。衬垫介电层24可利用本技术领域中几种常规的方法中的任何一种方法形成。非限制性例子包括热氧化方法、化学气相淀积法和物理气相淀积法。最好,衬垫介电层24利用热氧化方法形成以得到氧化硅材料。一般,衬垫介电层24具有从大约10到大约100埃的厚度。
应力传递层26可包含几种应力传递材料中的任何一种,但从实际可行的观点来看,应力传递材料必须具有阻热性能,其允许较高温度退火,而不破坏应力传递层或任何在其下方的层。应力传递材料的非限制性例子包括氮化硅材料和氮氧化硅材料。氮化硅材料特别优选。应力传递层26可以具有适用于n-finFET或p-finFET的正应力或者负应力。
同样从实际可行的观点来看,当形成应力传递层26时,可利用几个过程变量来影响应力。非限制性例子包括淀积温度、起始材料、淀积速度和厚度。一般,应力传递层具有从大约500到大约2000埃的厚度,尽管实施例和本发明都不受此限制。
图10显示的是对图9中所示半导体结构进行热退火的结果。随着热退火,局部非晶化栅电极22′再结晶以生成再结晶的栅电极22″。在当前的实施例中,局部非晶化栅电极22′的再结晶以生成再结晶的栅电极22″的过程同时涉及非晶化子层22b的再结晶以形成一个再结晶子层22b′的过程。当局部非晶化栅电极22′再结晶以生成再结晶的栅电极22″时,其(即尤其是针对非晶化子层22b来说)在应力传递层26的应力条件的影响下进行再结晶。因而,再结晶的栅电极22″在位于离半导体鳍片14a和刻蚀后的埋入介电层12′较近处的第一部分或区域(即在初始应力水平下形成的未非晶化的子层22a)中具有第一应力,在离半导体鳍片14a和刻蚀后的埋入介电层12′较远的分离的第二部分或区域(即再结晶子层22b′)具有不同于第一应力的第二应力。另外,在再结晶期间和与之伴生的热退火期间,在局部非晶化栅电极22′和半导体鳍片14a中包含的掺杂剂将在从应力传递层26传递到非晶化子层22b中的应力范围之内重新分布。这种掺杂剂重新分布的类型和机理也能增强finFET器件的性能。
至于再结晶的栅电极22′,其中的第一应力可小于第二应力或第一应力可大于第二应力。第一应力和第二应力可都是压缩性的或都是拉伸性的。可选择地,第一应力和第二应力中的一个可以是拉伸性的,而第一应力和第二应力中的另一个可以是压缩性的。
可利用半导体制造技术领域中常规的几种热退火方法中的任何一种来进行局部非晶化栅电极22′的再结晶以形成再结晶栅电极22″。非限制性例子包括炉内退火方法和快速热退火方法。一般,但并非排他性地,对局部非晶化栅电极22′以从大约1000℃到大约1200℃的温度进行热退火持续大约2到大约6个小时的时间。一般,热退火在惰性气体中进行,诸如氦气、氩气、氪气或氮气,尽管对这一点并不作要求。本领域的技术人员应理解,前述热退火条件也适用于半导体鳍片14a中的源极/漏极区域的再结晶和对植入其中的活性掺杂剂的驱动。
图11显示了从图10中所示半导体结构中依次剥离应力传递层26和衬垫介电层24的结果。在剥离后,它们暴露出再结晶栅电极22″。在使用半导体制造技术领域中常规的方法和材料的同时,它们被依次剥离。特别地,但并非加以限制,对于氮化硅或氧化硅材料,可采用磷酸水溶液材料。同样并非加以限制,对于氧化硅材料,可采用氢氟酸水溶液材料。也可利用其它合适的湿式化学刻蚀材料和干式离子刻蚀材料。
图11显示了在第一种情况下根据本发明优选实施例的半导体结构。在第一种情况下,所述半导体结构包括在刻蚀后的埋入介电层12′之中的基座13上对齐的半导体鳍片14a。基座13使得半导体鳍片14a与刻蚀后的埋入介电层12′的周围部分隔离开。由于隔离,依次地设置并且形成于半导体鳍片14a上的再结晶的栅电极22″具有更完整的覆盖面(more complete overlap)。在根据图11的finFET结构之中,再结晶的栅电极22″具有多个不同应力的区域。这些区域包括位于离半导体鳍片14a较近处并具有第一应力的第一区域,同时具有离半导体鳍片14a较远处并具有不同于第一应力的第二应力的第二区域。
尽管优选实施例以具有两个不同应力区域的再结晶栅电极22″说明了本发明,但是当前的实施例和本发明都并非受此限制。相反地,本领域技术人员应理解,本发明可通过用深度依次越来越小的栅电极的离子注入非晶化,并在多个依次应力传递层作用下伴随着并行的和依次的再结晶化来实施。前述的工艺步骤在多个再结晶栅电极之中进一步生成额外限定的应力区域。
图12显示了一个示意性平面视图,示出了对图11中所示finFET更进一步处理的结果。图12也与图5对应,但具有一对位于半导体鳍片层14a上没有被再结晶的栅电极22″覆盖的源极/漏极区域之上的硅化物层28。为了提供与图5中所示finFET结构相似的图12中的finFET结构,位于半导体鳍片14a区域上没有被再结晶栅电极22″覆盖的图案化硬掩模层16a被部分移除。它们可用半导体制造技术领域中常规的刻蚀方式移除。所述方法包括,但不仅限于:湿式化学刻蚀方法和干式离子刻蚀方法。
一旦半导体鳍片14a的源极/漏极区域部分被暴露,可用也是本技术领域中常规的方法形成这对硅化物层28。一般,这对硅化物层28是利用金属硅化物形成金属层淀积、热退火以及后续的无反应金属刻蚀方法(即自对准多晶硅化物方法)形成的。可以采用其它方法。典型的金属硅化物成形金属包括,但不仅限于:钨、钴、铂、镍和钛。一般,热退火条件是以大约350℃到大约850℃的温度持续从大约1秒钟到大约10分钟的时间。未反应的金属刻蚀剂专门用于特殊金属并且一般为湿式化学刻蚀剂,尽管这不是发明的要求。一般,这对硅化物层28中的每一个都具有从大约50到大约300埃的厚度。它们在本发明中是任选的。
图13显示了对图11或图12中所示半导体结构的更进一步处理结果,因为如图12所示的这对硅化物层28在本发明中是任选性的。图13显示了位于再结晶栅电极22″之上的第二应力传递层30。第二应力传递层30可包含与用于应力传递层26的那些应力传递材料类似的、相同的或等同的应力传递材料。它也可利用类似的、相同的或等同的方法形成。一般,第二应力传递层具有从大约200到大约1000埃的厚度。
在当前的实施例中,第二应力传递层30可具有不同于下述应力中任何一个的第三应力:(1)再结晶栅电极22″中的未非晶化子层22a内部的离半导体鳍片14a较近的第一应力;或(2)再结晶栅电极22″中的再结晶子层22b′内部的离半导体鳍片14a较远的第二应力。第一应力、第二应力和第三应力可定义一个连续的应力级数(要么增大要么减小)。或者,它们可定义一个不连续的应力级数。第一应力、第二应力和第三应力中的每一个可互相独立地为拉伸应力或压缩应力。第一应力、第二应力和第三应力的大小也可变化,但典型的范围从大约-3.5GPa到2.5GPa。
图13显示了进一步根据本发明优选实施例的半导体结构。这种半导体结构包括具有再结晶栅电极22″的finFET结构,其中再结晶栅电极22″在位于离其中的半导体鳍片14a较近处的第一区域(即未非结晶型子层22a)中具有的第一应力,并且在位于离半导体鳍片14a较远处的第二区域(即再结晶子层22b′)中具有不同于第一应力的第二应力。所述finFET结构还包含位于再结晶栅电极22″上面的应力传递层30。应力传递层30可具有既不同于第一应力也不同于第二应力的第三应力。根据本实施例在finFET中的再结晶栅电极22″的多个部分内部的不同应力水平,有助于调节finFET中的半导体鳍片14a内部的应力。进而,这可以提供增强的finFET性能。
本发明的优选实施例是为了说明本发明而不是对本发明加以限制。在仍旧根据本发明提供实施例或者进一步地根据所附权利要求提供实施例的同时,可以对根据本发明优选实施例的方法、材料、结构和尺寸进行修正和改动。
Claims (20)
1、一种结构,包括:
位于衬底上面的半导体鳍片;
位于半导体鳍片上面的栅电极,该栅电极在位于离半导体鳍片较近处的第一区域中具有第一应力,并且在位于离半导体鳍片较远处的第二区域中具有不同于第一应力的第二应力。
2、如权利要求1所述的结构,其特征在于,所述衬底是绝缘体上半导体衬底。
3、如权利要求1所述的结构,其特征在于,所述半导体鳍片包含从由Si、SiC、SiGe、SiGeC、Ge、GaAs、InAs、InP、其它III-V或II-VI化合物半导体材料以及有机半导体材料构成的组中选取的半导体材料。
4、如权利要求1所述的结构,其特征在于,所述第一应力和第二应力形成应力梯度。
5、如权利要求1所述的结构,其特征在于:所述第一应力和第二应力属于相反类型。
6、如权利要求1所述的结构,其特征在于,所述半导体鳍片位于衬底内部的基座上面。
7、如权利要求1所述的结构,其特征在于,所述半导体鳍片在衬底内部的基座上面对齐设置。
8、如权利要求1所述的结构,还包括位于所述栅电极上面的应力传递层。
9、如权利要求1所述的结构,其特征在于,所述应力传递层具有不同于第二应力和第一应力的第三应力。
10、一种结构,包括位于衬底内部的基座上面的半导体鳍片。
11、如权利要求10所述的结构,其特征在于,所述半导体鳍片在衬底内部的所述基座上面对齐设置。
12、如权利要求10所述的结构,其特征在于,所述半导体鳍片是硅半导体鳍片。
13、如权利要求10所述的结构,其特征在于,所述基座在所述衬底内部具有从大约300到大约500埃的高度。
14、一种制造一种结构的方法,包括:
在衬底上面形成半导体鳍片;和
在半导体鳍片上面形成栅电极,该栅电极在位于离半导体鳍片较近处的第一区域中具有第一应力,并且在位于离半导体鳍片较远处的第二区域中具有不同于第一应力的第二应力。
15、如权利要求14所述的方法,其特征在于,所述衬底是绝缘体上半导体衬底。
16、如权利要求14所述的方法,所述半导体鳍片包含从由Si、SiC、SiGe、SiGeC、Ge、GaAs、InAs、InP、其它III-V或II-VI化合物半导体材料以及有机半导体材料构成的组中选择的半导体材料。
17、如权利要求14所述的方法,其特征在于,所述第一应力和第二应力形成应力梯度。
18、如权利要求14所述的方法,其特征在于:所述第一应力和第二应力属于相反类型。
19、如权利要求14所述的方法,其特征在于,所述半导体鳍片被形成在衬底内部的基座上面。
20、如权利要求14所述的方法,其特征在于,所述半导体鳍片被制成在衬底内部的基座上面对齐设置。
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US7564081B2 (en) | 2009-07-21 |
JP5186101B2 (ja) | 2013-04-17 |
US20070120154A1 (en) | 2007-05-31 |
US8058157B2 (en) | 2011-11-15 |
US20090280626A1 (en) | 2009-11-12 |
JP2007158329A (ja) | 2007-06-21 |
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